Lab 7 - EE 421L

Date modified: November 07, 2018

Lab Description

This lab teaches how to utilize buses to create more clean schematics. This lab includes digital design with NOR, NAND, AND, and OR gates, inverters, MUXes, and Full Adders.

Pre-Lab objectives

Finish Tutorial 5.

Pre-Lab

After completing Tutorial 5, you should wind up with the schematic, layout, and simulation of a ring oscillator as seen below:

Prelab Schematic

As usual, make sure that the layout DRC and LVS's properly.

This ends the content of the Prelab.

Lab objectives

Create and simulate a 4-wide parallel inverter array.

Comment on the effect of the load capacitors.

Create scheamtics and symbols for NAND, NOR, AND, and OR gates.

Run these gates in parallel (8-wide) to create new 8-bit gates.
Create simulations to demonstrate the operation of these gates.

Create the schematic and symbol for a 2-1 MUX/DEMUX.

Run these MUXes in parallel (8-wide) to create an 8-bit word MUX/DEMUX.
Show how the circuit can be used for both multiplexing and demultiplexing.
Include an inverter so that only the S input is needed (Si is the compliment of S, henc the inverter).
Create a simulation to show the operation of the 8-bit MUX/DEMUX.

Create a scheamtic and symbol for a Full Adder according to Fig. 12.20 (using 6u/0.6u devices).

Run these Full Adders in series (8-long) to create an 8-bit Full Adder.
Layout both the single Full Adder and the 8-bit Full Adder.

Ensure that the layouts LVS and DRC properly.

Create a simulation to show the operation of the 8-bit Full Adder.

Lab

4-bit Inverter

The schematic and symbol for the 4-bit parallel inverter can be seen below:

4-bit Inverter Schematic

4-bit Inverter Symbol

The simulation schematic for analyzing the operation of this 4-bit inverter is shown below:

4-bit Inverter Simulation Schematic

Results from this simulation can be seen below:

4-bit Inverter Sim Results

Note that as the load capacitance decreases, the faster the rise-time.

8-bit NAND

Below shows the schematic and symbol of the 1-bit NAND gate:

1-bit NAND Schematic

1-bit NAND Symbol

The schematic and symbol for the 8-bit NAND gate can be seen below:

8-bit NAND Schematic

8-bit NAND Symbol

8-bit NOR Gate

The schematic and symbol for the 1-bit NOR gate can be seen below:

1-nit NOR Schematic

1-bit NOR Symbol

The 8-bit schematic and symbol for the NOR gate can be seen below:

8-bit NOR Schematic

8-bit NOR Symbol

8-bit AND Gate

The schametic and symbol for the 1-bit AND gate can be seen below:

1-bit AND Schematic

1-bit AND Symbol

The 8-bit schematic and symbol for the AND gate can be seen below:

8-bit AND Schematic

8-bit OR Gate

The schematic and symbol for the 1-bit OR gate can be seen below;

1-bit OR Schematic

1-bit OR Symbol

The 8-bit schematic and symbol for the OR gate can be seen below:

8-bit OR Schematic

8-bit OR Symbol

8-bit Inverter

The schematic and symbol for the 8-bit inverter can be seen below:

8-bit Inverter Schematic

8-bit Inverter Symbol

8-bit Gates Simulation:

The schematic and results of the simulation for the collection of 8-bit gates can be seen below:

8-bit Gates Simulation Schematic

8-bit Gates Simulation Abar

Note that the result of Abar is: 11001100 for an input of 00110011.

8-bit Gates Simulation AandB

Note that the result of AandB is: 00100010 when A = 00110011 & B = 11101010.

8-bit Gates Simulation AorB

Note that the result of AorB is: 11111011 when A = 00110011 & B = 11101010.

8-bit MUX/DEMUX

The schematic and symbol for the 2-to-1 MUX/DEMUX is shown below:

2-to-1 MUX/DEMUX Schematic 2-to-1 MUX/DEMUX Symbol

Note that this design can work as either a MUX or DEMUX.

The schematic and symbol for the 8-bit wide MUX is shwon below:

8-bit MUX/DEMUX Schematic

Note that an inverter was used to feed directly into Si, elimnating a need for it as an input pin in the future.

8-bit MUX/DEMUX Symbol

Finally, the simulation schematic and results for the 8-bit MUX choosing between two 8-bit words (A = 00110000 & B = 11001100) using the selection input S: