Lab 6 - EE 421L

Date modified: October 28, 2018

Lab Description

This lab shows how to create layouts, schematics, and simulations of NAND and XOR gates and a Full Adder. These were created using 6u/600n MOSFETS.

Pre-Lab objectives

Finish Tutorial 4.

Pre-Lab

After completing Tutorial 4, you should wind up with the schematic, symbol, and layout of a NAND gate as seen below:

Prelab NAND Schematic

Next you should DRC, extract, and LVS the NAND gate:

Prelab NAND DRC

Finally, the following schematic and simulation results should be obtained:

Prelab NAND Sim Schematic

This ends the content of the Prelab.

Lab objectives

Draft the schematics of a 2-input NAND gate, and a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS).

Create layout and symbol views for these gates showing that the cells DRC and LVS without errors

Ensure that the symbol views are the commonly used symbols (not boxes!) for these gates with your initials in the middle of the symbol .
Ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
Use a standard cell height taller than needed for these gates so that it can be used for more complicated layouts in the future.
Ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1.

Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11).

Comment on how timing of the input pulses can cause glitches in the output of a gate.

Using these gates, draft the schematic of a full adder.

Create a symbol for this full-adder.
Simulate, using Spectre, the operation of the full-adder using this symbol .

Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed.

Full-adder inputs and outputs can be on metal2 but not metal3.
DRC and LVS the full adder design.

Lab

NAND Gate

See the content of the Prelab for the schematic, symbol, layout, and simulation for the NAND gate.

XOR Gate

The schematic, layout, and symbol for the XOR gate are shown below:

XOR Schematic

        XOR Layout

      XOR Symbol

    Next you should DRC, extract, and LVS the XOR gate:

            XOR DRC

             XOR LVS Parameters         XOR LVS Success

Finally, the following schematic and simulation results should be obtained:

    XOR Sim Schematic

    XOR Sim Results

Full Adder

The schematic, layout, and symbol for the Full Adder are shown below:

Full Adder Schematic

        Full Adder Layout

      Full Adder Symbol

    Next you should DRC, extract, and LVS the Full Adder:

            Full Adder DRC

             Full Adder LVS Parameters         Full Adder LVS Success

Finally, the following schematic and simulation results should be obtained:

    Full Adder Sim Schematic

    Full Adder Sim Results

As seen in this simulation image above, some "glitches" can be seen in the output of the Full Adder. These glitches are due to the rise/fall time of the adders, causing some MOSFETS to be neither ON or OFF at the given time.
This can be fixed by increasing the capactiance of the decoupling capacitor(s) on the outputs.

This concludes the main content for Lab 6.

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