Lab 5 - EE 421L 

Author: Dylan Wallace

Email: wallad3@unlv.nevada.edu

Date modified: October 10, 2018

  

Lab Description

   This lab shows how to create layouts, schematics, and simulations of CMOS inverters. Two CMOS inverters, 12u/6u and 48u/24u, were created in this lab.

Pre-Lab objectives

Pre-Lab

    After completing Tutorial 3, you should wind up with the schematic, symbol, and layout of a CMOS inverter as seen below:


        Prelab Schematic          Prelab Layout

        Prelab Symbol


    Next you should DRC, extract, and LVS the inverter:


            Prelab LVS Parameters        Prelab LVS Success


    Finally, the following schematic and simulation results should be obtained:


        Prelab Sim Schematic

        Prelab Sim Results

     

    This ends the content of the Prelab.

Lab objectives

Lab

   Schematics

        The schematics of the 12u/6u (left) and 48u/24u (right) inverters are shown below:


           Inverter Schematic 1        Inverter Schematic 2


        As can be seen, the 48u/24u inverter is a 4-finger version of the 12u/6u inverter.

   

   Symbols

        The symbols representing our schematic are shown below:

         

            Inverter Symbol 1

           Inverter Symbol 2

       These symbols represent the typical symbol for the NOT gate, which is an inverter.

   Layouts

        The layouts for the 12u/6u (left) and 48u/24u (right) are shown below:


            Inverter Layout 1        Inverter Layout 2


        As seen in these images, the top and bottom are used to run Vdd and Gnd, respectively.

        The DRC results of each layout are shown below:

           Inverter DRC 1        Inverter DRC 2

        The extracted views for both the 12u/6u (left) and 48u/24u (right) are shown below:

            Inverter Extracted 1        Inverter Extracted 2


        The LVS parameters and results for both the 12u/6u (left) and 48u/24u (right) inverters are shown below:

         
            Inverter LVS Params 2        Inverter LVS Params 2

           Inverter LVS Results 1                              Inverter LVS Results 2


   Simulations

        12u/6u Inverter:

            The schematic for the simulation of the 12u/6u inverter is shown below:

        

                Inverter Sim Schematic 1

            As seen in the image, a variable was used for the capactior value. We will sweep this value by decade from 100fF to 100pF to demonstrate the operation of the CMOS inverter. To acheive this, we will add a variable to the ADE L, as seen below:

                Inverter Sim Var

            We will run a transient analysis from t = 0 to t = 25 ns. Additionally, we need to add the NMOS and PMOS models to the simulator, as seen below:

                Inverter Sim Models

            Finally, we can perform a parametric analysis on the CapVal variable, as seen below:

                Inverter Sim Parametric

            The Spectre results of this analysis can be seen below:

        

                Inverter Sim Spectre 1

            As seen in this image, the coupling capactior reduces the rate of response of the inverter (i.e. the rise/fall time).

            Make sure to save the Spectre state. Now we will run the simulation using UltraSim. Change the simulator by going to Simulator/Directory/Host, and choosing UltraSim, as seen below:

                Inverter Sim UltraSim

            Repeat the steps for adding the models and running the parametric analysis as in the Spectre case. The reults of the UltraSim simulation can be seen below:

                Inverter Sim UltraSim 1

            The UltraSim results do run faster than Spectre, but the increased efficiency is not as easily seen as our simulation isn't too large.

        48u/24u Inverter:

            The schematic for the 48u/24u inverter can be seen below:

                Inverter Sim Schematic 2

            Again, we will use the CapVal variable to run a parametric analysis. We will repeat the steps for adding the models, variable, and running the parametric analysis. The results of the Spectre simulation can be seen below:

                Inverter Sim Spectre 2

            As seen in this image, the effects of the coupling capacitor are reduced with the 48u/24u inverter, due to the increased power output.

            The results for the UltraSim can be seen below:

                Inverter Sim UltraSim 2

    Zip Files

          The zip files for the content of this lab can be accessed here: lab5_dw.zip.

    This concludes the main content for Lab 5.


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