Lab 5 - EE 421L
Authored
by Marco Muniz,
Email: munizm1@unlv.nevada.edu
09/30/2018
Prelab
Complete Tutorial 3 and show completed work.
![file:///C:/Users/mmuni/Pictures/Lab%205/Prelab_inverter_Schematic.JPG](Prelab_inverter_Schematic.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/Prelab_inverter_Sim.JPG](Prelab_inverter_Sim.JPG)
Above, we can see the completed inverter layout along with the drafted schematic that shows input-to-output simulation.
Lab
For the main lab, we must complete the following steps:
- Draft schematics, layouts, and symbols for two inverters having sizes of:
- 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
- 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET
- Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
- Comment, in your report, on the results
- Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations
Part 1
12u/6u Inverter (m = 1) :
![file:///C:/Users/mmuni/Pictures/Lab%205/12_6_Extracted.JPG](12_6_Extracted.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/12_6_Symbol.JPG](12_6_Symbol.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/12_6_LVS.JPG](12_6_LVS.JPG)
48u/12u Inverter (m = 4) :
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_Extracted.JPG](48_24_Extracted.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_Symbol.JPG](48_24_Symbol.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_DRC.JPG](48_24_DRC.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_LVS.JPG](48_24_LVS.JPG)
___________________________________________________________________________________________________________________________________
Part 2
Schematic and Spice Simulations for Inverters driving 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
12u/6u Inverter
48u/12u Inverter
![file:///C:/Users/mmuni/Pictures/Lab%205/48u_24u_Schematic.JPG](48u_24u_Schematic.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/Parametric_Settings.JPG](Parametric_Settings.JPG)
In
the images above, we can see that Spectre has been set as the simulator
and the settings used to run the Parametric Analysis for the Various
Capacitive Load.
12u/6u Inverter Specter Simulation
![file:///C:/Users/mmuni/Pictures/Lab%205/12_6_Spectre_sim1.JPG](12_6_Spectre_sim1.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/12_6_Spectre_sim2.JPG](12_6_Spectre_sim2.JPG)
48u/24u Inverter Specter Simulation
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_Spectre_sim1.JPG](48_24_Spectre_sim1.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_Spectre_sim2.JPG](48_24_Spectre_sim2.JPG)
__________________________________________________________________________________________________________________________________
Part 3
For
the last part, we will repeat the above simulations but now using
Ultrasim (Cadence's fast SPICE simulator for larger circuits at the
cost of accuracy)
![file:///C:/Users/mmuni/Pictures/Lab%205/Ultrasim_Settings.JPG](Ultrasim_Settings.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/Parametric_Settings.JPG](Parametric_Settings.JPG)
In
the images above, we can
see that now UltraSim has been set as the simulator. We will also be
using the same Parametric Analysis Set-up to see the how the various
Capacitive Loads affect the Inverters.
12u/6u Inverter UltraSim Simulation
![file:///C:/Users/mmuni/Pictures/Lab%205/12_6_Ultrasim_sim1.JPG](12_6_Ultrasim_sim1.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/12_6_Ultrasim_sim2.JPG](12_6_Ultrasim_sim2.JPG)
48u/24u Inverter UltraSim Simulation
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_Ultrasim_sim1.JPG](48_24_Ultrasim_sim1.JPG)
![file:///C:/Users/mmuni/Pictures/Lab%205/48_24_Ultrasim_sim2.JPG](48_24_Ultrasim_sim2.JPG)
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