Lab 5 - EE 421L
Authored
by Marco Muniz,
Email: munizm1@unlv.nevada.edu
09/30/2018
Prelab
Complete Tutorial 3 and show completed work.
Above, we can see the completed inverter layout along with the drafted schematic that shows input-to-output simulation.
Lab
For the main lab, we must complete the following steps:
- Draft schematics, layouts, and symbols for two inverters having sizes of:
- 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
- 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET
- Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
- Comment, in your report, on the results
- Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations
Part 1
12u/6u Inverter (m = 1) :
48u/12u Inverter (m = 4) :
___________________________________________________________________________________________________________________________________
Part 2
Schematic and Spice Simulations for Inverters driving 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
12u/6u Inverter
48u/12u Inverter
In
the images above, we can see that Spectre has been set as the simulator
and the settings used to run the Parametric Analysis for the Various
Capacitive Load.
12u/6u Inverter Specter Simulation
48u/24u Inverter Specter Simulation
__________________________________________________________________________________________________________________________________
Part 3
For
the last part, we will repeat the above simulations but now using
Ultrasim (Cadence's fast SPICE simulator for larger circuits at the
cost of accuracy)
In
the images above, we can
see that now UltraSim has been set as the simulator. We will also be
using the same Parametric Analysis Set-up to see the how the various
Capacitive Loads affect the Inverters.
12u/6u Inverter UltraSim Simulation
48u/24u Inverter UltraSim Simulation
Link to Lab 5 Directory Files:
Lab 5 Zip
Return To My Lab's
Return to Student Directory
Return to CMOS Home