Lab Project - ECE 421L
The first component that was made was an inverter made with a pmos and nmos transistor with the same W/L ratio. The inverter has both gates tied to gother with the input put and the drain of the pmos tied together with the drain of the nmos, where the source and body of the pmos and nmos is tied to vdd and ground respectivly. This means when the input is high the pmos is turned off and the nmos is turned on pulling the output to ground. When the input is low the pmos is on and the nmos is on pulling the output high.
Image 1:Inverter Schematic
Following the schematic creation the next step was to make a symbol for the inverter to simplify future designs that would use the logic gate.
Image 2:Inverter Symbol
After making the Inverter symbol the next step was to make a layout view of the inverter using the same width and length of nmos and pmos. They were placed using 4 grid units about the axis for the pmos and 4 below for the nmos to allign the larger layouts later on.
Image 3:Inverter Layout view
To ensure that the layout was made properly a design rule check or DRC was used, after the DRC an LVS was used which checks that the layout matches same nodes as the schematic.
Image 4:Inverter LVS and DRC respectivly
Following the creation of the inverter the next step was to create a transistor gate using an nmos and pmos with the same W/L ratio. Both the sources are tied together and both of the drains are also tied together, with the body of the nmos tied to vdd and the body of the nmos tied to ground. The gate of the pmos is tied to an input S and the gate of the nmos is tied to S_not. Both of the tied sources and drains are connected to an input/output pin.
Image 5:Transistor gate schematic
After making the schematic for the transistor gate the symbol view was made to also simplify the circuit for future designs.
Image 6:Transistor gate symbol
After making the sybol view of the transistor gate the layout view was made and design rule checked with the LVS to ensure it was created correctly.
Image 7:Transistor gate Layout
Image 8:Transistor gate LVS and DRC
Following making the transistor gate a D flip flop was made using both previously mentioned components. The D flip flop was made using three transistor gates and four inverters.
Image 9:D flip flop schematic
In order to ensure that it was made correctly three voltage sources were made to simulate the clock the inverted clock and the vdd for the pmos and nmos transistors. For the D flip flop every time the clock trigger occurs the output Q will become the same value of D and Q_not will become the opposite.
Image 10:D flip flop simulation
After ensuring that the D flip flop was running properly a symbol view was made to once again simplify future schematics that need the D flip flop.
Image 11:D flip flop symbol
Following making the D flip flop schematic and symbol the next part was to make the layout view, since we made the trans gate and inverters previously we are able to just istantiate the components instead of making them individually. After istantiating the components in the following step was to wire the correct outputs to the correct inputs, according to the schematic we made earlier.
Image 12:D flip flop layout view
The next step is to use the DRC and LVS tools to ensure that it follows the design rules and that all nodes are correctly matching the same node in the schematic.
Image 13:D flip flop LVS and DRC
After creating the D flip flop the next step was to make a time shifting component to compensate for the differnt clocks needed for the different D flip flops. This was done using three d flip flops where the input goes to the first D flip flop clock the D and Q_not are tied together and the Q feeds into the next D flip flop clock input, until the last Q is the shifted clock output. This circuit takes the input clock and then extends the time spent high and overall period time.
Image 14:Time shift schematic
To ensure that the time shift is working properly a clock input was made using for a voltage pulse source and a vdc used for the vdd value for all the nmos and pmos that need it.
Image 15:Time shift simulation
The next step was to create the layout view of the time shift component which was significantly shortened by istantiating the d flip flop we made earlier into the layout three times. After wiring them correctly the DRC and LVS tools were used to once again ensure that the the design rules were followed and the nodes match the corresponding schematic nodes.
Image 16:Full time shift layout
Because the time shift layout is so large here are two closer views showing the input pins of the time shift and another image showing the output pins.
Image 17:Input pins of time shift layout
Image 18:Output pins of time shift layout
After making the time shift component all the components that are needed to creat the serial to parallel converter are made and can begin being created. For this circuit we are told that there will be two inputs being the clock input and the serial input, in addition to this there are 9 outputs being a clock output, and the 8 d flip flop outputs. The total circuit use 8 D flip flops for the shift register and 8 d flip flops to store the values given to the shift registers.
Image 19:Serial to parallel converter schematic
To simulate this circuit the two previously mentioned inputs were made using two vpulse sources and as before a vdc was used for all the pmos and nmos that needed a vdd source. To know this works the ouput should mimic the input based on the clock triggers.
Image 20:Serial to parallel converter simulation results.
After the simulation was ran the layout view was made next using istantiated parts from all the previous parts that we have made, significantly lowering the time of the creation.
Image 21:Full serial to parallel converter layout view
Like the time shift the serial to parallel converter is such a large layout view the input and output were zoomed into so that they were visable.
Image 22:Input pins of the serial to parallel converter layout view
