Lab 7 - ECE 421L 

Author:    Nicholas Mingura

Email:       mingura@unlv.nevada.edu

Prelab:

For the prelab the main goal was to make the ring ocsillator using inverters and showing the out put of the schematic. 

Image 1:Ring Oscillator Schematic

Image 2: Ring Oscillator Simulation

After running the simulation of the ring oscillator to know that it was running properly the layout view was needed, below is a zoomed in version of the layout where the circuit repeats until the end.

Image 3: Ring Oscillator Layout

After making the layout view it went through the DRC and LVS operations to ensure that it was made correctly and matched the schematic. 

Image 4:Ring Oscillator DRC

Image 5:Ring Oscillator LVS

Lab:

For the lab, the main goal was to make an eight bit full adder and all the components that are necassry to make it. From the previous lab the class has some of the gates made in a two bit version and just needed to be converted to make the eight bit version. 

To start the lab off a four bit inverter was made to show how to use two bit symbols to make multiple bit circuits in a simple manner. In the fist image we can see the original way that the class would have made the four bits by laying out four individual inverters and then making individual lines for each of them. 

Image 6: Four bit inverter circuit without simple short cut.

In this lab, we learned that instead on a schematic you can change the instance name to Io<x,0> where x is the amount of instances you need minus one, and then draw a bus line and label the bus to do the same job in a compact form. 

Image 7: Four bit inverter circuit using simple short cut.

After creating the more compact four bit inverter the circuit was used in a circuit to show that the compact manner works the same. 

Image 8: Four bit inverter schematic for simulation

Image 9: Four bit inverter simulation showing correct opperation 

After making the four bit inverter, the next task was to make an eight bit inverter which was implemented the same way just with differnt labeling of the bus wire and the amount of instances of inverter. Following making the inverter the next step was to make an eight bit nand gate, this goal was achieved by istantiating a two bit nand gate made in the previous lab and then changing the instances to <7:0> and then labeling the bus wires. After making the eight bit nand gate the cell view was used to make a symbol view and placed inside of a circuit to show that set inputs would give the correct outputs. This step was then repeated for an eight bit and, nor, & or gates so that the full adder could be built. In the previous lab, we did not make the and or the or gate so to make these the inverter was put following the nand and nor gate respectively to get the correct results. These images can be seen in the table below.

	Schematic	Symbol	Simulation Schematic	Simulation Results
NAND
NOR
AND
OR
Not

After creating these gates, the lab gave a two bit demux/mux schematic. This circuit can be used either way seen in the simulations below, and works by the getting four inputs a, b, s, and si. S and si are used to alternate between various input or outputs that you want, in the demux they dictate whether a or b will be used for an input to the given output, for the mux they decide which output the single input will go to. 

Image 10:Demux/mux Schematic.

Image 11:Demux/mux Simulation

Image 12:Demux/mux eight bit schematic

Image 13:Demux/mux eight bit symbol.

Finally, after making the eight bit demux/mux the final step is to make the full adder schematic and simulation. Seen below is a schematic of a 2 bit full adder circuit which was converted to a symbol like the precious gates and with busses made to an eight bit full adder. The real difficulty of the 8 bit full adder is that the layout view doesnt use busses and needs to be wired exactly. This was achieved by putting an input pin for every a<7:0> and b<7:0> a single cin and a single cout, where the cin input goes to the first full adder and that cout goes to the second full adder cin which reapeats until the last full adder where the last cout goes to a cout pin. 

Image 14: Full adder two bit operation schematic

Image 15: Full adder eight bit full schematic

Image 16: Full adder eight bit symbol view

Image 17: Full adder eight bit simulation schematic

Image 18: Full adder eight bit simulation results.

The layout view for the full adder is very large and can not be seen in one picture so it will be broken up into three photos in addition with the LVS and DRC.

Image 19:Full adder DRC

Image 20:Full adder LVS

Image 21:Left half of full adder

Image 22:Right half of full adder

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