Lab 5 - ECE 421L 

Author:    Nicholas Mingura

Email:       mingura@unlv.nevada.edu

   

For the prelab the students were tasked with finishing tutorial 3 which was building an inverter with a 12u/.6u pmos and a 6u/.6u nmos. This inverter was required to be built for the main section of the lab along with another slight variant on the inverter. 

    

   

file:///C:/Users/oit/Desktop/Lab_5_Photos/Prelab_inverter_schematic.JPG   file:///C:/Users/oit/Desktop/Lab_5_Photos/Prelab_inverter_symbol.JPG

Image 1: Prelab/First lab Inverter schematic and symbol 

  

After making the inverter and symbol the layout view was made using the same dimension pmos and nmos. 

        
       
file:///C:/Users/oit/Desktop/Lab_5_Photos/Prelab_inverter_layout.JPG

Image 2: Prelab/First lab Inverter layout

   

  

 file:///C:/Users/Nicholas/Desktop/EE%20421L/Lab%205/Inverter_LVS.JPGfile:///C:/Users/Nicholas/Desktop/EE%20421L/Lab%205/Inverter_DRC.JPG

Image 3: DRC and LVS of prelab inverter schematic and extracted 


Following the layout view the symbol made for the inverter is used in a circuit to test that the inverter is operating as expected. After testing the schematic the enviorment options was opened and edited so that the extracted layout view would be tested to show that the layout was functioning properly as well. 

     
     
Image 4: Schematic testing prelab inverter operation
   
 
file:///C:/Users/Nicholas/Desktop/EE%20421L/Lab%205/Inverter_Sim_Fixed.JPG  file:///C:/Users/Nicholas/Desktop/EE%20421L/Lab%205/Inverter_Extracted_Sim.JPG
Image 5: Graph of prelab inverter layout operation, extracted operation
   
   
After completing the prelab the main lab only requires you to make one more inverter with the same width and lengths on the pmos and nmos but to give them both a multiplier of 4. After recreating the inverter we redid all of the previous steps for the second inverter.
 
 
file:///C:/Users/oit/Desktop/Lab_5_Photos/Lab_inverter_schematic.JPG   file:///C:/Users/oit/Desktop/Lab_5_Photos/Lab_inverter_symbol.JPG
Image 6: Second inverter schematic and symbol
 
 
file:///C:/Users/oit/Desktop/Lab_5_Photos/Lab_inverter_layout.JPG
Image 7: Second inverter layout
 
 
file:///C:/Users/Nicholas/Desktop/EE%20421L/Lab%205/Inverter_2_LVS.JPG
Image 8:DRC and LVS of second inverter schematic and extracted
   
 
For the next part of the lab the students were tasked at testing our inverters with multiple differnt capacitance vaules on a ciruit, which was done using a parametric anaylsis and the ultra sim feature in cadence.
 
 
file:///C:/Users/oit/Desktop/Lab_5_Photos/First_inverter_cap_schematic.JPG
Image 9: Schematic of first inverter tesing with multiple differnt valued capacitors.
   
   
file:///C:/Users/oit/Desktop/Lab_5_Photos/First_inverter_cap_sim.JPG  file:///C:/Users/oit/Desktop/Lab_5_Photos/First_inverter_cap_sim_input.JPG
Image 10: Simulation of first inverter using parametric analysis with varying capacitance values, and the input.
   
  
file:///C:/Users/oit/Desktop/Lab_5_Photos/First_inverter_cap_ultrasim.JPG  file:///C:/Users/oit/Desktop/Lab_5_Photos/First_inverter_cap_ultrasim_input.JPG  
Image 11: Ultra sim of first inverter using parametric analysis with varying capacitance values, and input.
 
 
file:///C:/Users/oit/Desktop/Lab_5_Photos/Second_inverter_cap_schematic.JPG
Image 12: Schematic testing second inverter operation with carying capacitance values.
 
 
file:///C:/Users/oit/Desktop/Lab_5_Photos/Second_inverter_cap_sim.JPG  file:///C:/Users/oit/Desktop/Lab_5_Photos/Second_inverter_cap_sim_input.JPG
Image 13: Simulation of second inverter using parametric analysis with varying capacitance values, and the input.
 
 
file:///C:/Users/oit/Desktop/Lab_5_Photos/Second_inverter_cap_ultrasim.JPG  file:///C:/Users/oit/Desktop/Lab_5_Photos/Second_inverter_cap_ultrasim_input.JPG
Image 14: Ultra sim of second inverter using parametric analysis with varying capacitance values, and the input.

Lab_5_zip

 

 

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