Lab 4 - ECE 421L
Author: Nicholas Mingura
Email: mingura@unlv.nevada.edu
09/26/2018
Pre-Lab
For
the prelab the class was tasked at completing tutorial 2 in order to
understand NMOS and PMOS schematic and layouts. After completing these
schematic and layouts for each we were to simulate the IV curve and to
back up our files.
Image 1: Pre-lab NMOS schematic, PMOS schematic.
Image 2: Layout view of NMOS, PMOS
Lab
The
first part of the lab is broken down into four differnt parts two using
NMOS and two using PMOS that the class built in the prelab. The first
NMOS schematic and simulation that we made was for an
NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies
from 0 to 5 V in 1 mV steps, with a 6u/600n width-to-length ratio. For
the second NMOS experiment the class was for an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps, using a 6u/600n width-to-length ratio.The schematic view of the NMOS with the width-to-length ratio can be seen in Image 1.
Image 3: Simulation of NMOS where VGS varyies from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps.
Image 4: Simulation of NMOS where VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps.
For
the PMOS transistors, like the NMOS transistors, the same
width-to-length raios were used where the PMOS raitio was 12u/600n. The
Schematic for the PMOS transistor can also be seen in Image 1. For the
first simulation we have a PMOS device for VSG varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps, and the second simulation is a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.
Image 5: Simulation of PMOS where VSG varyies from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps.
Image 6: Simulation of PMOS where VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.
The second part of the lab was to take the NMOS we made in the prelab and connect probepads to all 4 MOSFET terminals.
Image 7: Schematic of NMOS with all 4 terminals connected to a probe pad.
Image 8: Layout view of the NMOS with all 4 terminals connected to a probe pad.
Image 9: DRC and LVS of Layout of NMOS with all 4 terminals connected to a probe pad.
Finally, the last portion of the lab was to make the PMOS made in the prelab and connect probepads to all 4 MOSFET terminals.
Image 10: Schematic of PMOS with all 4 terminals connected to a probe pad.
Image 11: Layout view of the PMOS with all 4 terminals connected to a probe pad.
Image 12: DRC and LVS of Layout of PMOS with all 4 terminals connected to a probe pad.
Return to Nicholas Mingura's Labs
Return to EE 421L Students
Return to EE 421L Home