For the prelab the class was tasked with completing tutorial one by making a 10k resistor using the layout view. This required the use and knowledge of the n-well, metal contacts, p-well, and pins.
Image 1: Layout view of voltage divider from tutorial 1.
After making the layout view for the voltage divider the DRC function was used to make sure that there were no errors with the rules. Then the LVS was used to ensure that the netlist of the schematic and the extracted layout matched.
Image 2: LVS confirming that the net-lists match from the extracted layout and the schematic.
Lab:
For this lab the class was tasked with making a 10-bit digital to analog converter(DAC) using the 10k resistors that were made in the prelab. In tutorial 1 the circuit diagram shows that in order to make the 10-bit DAC a total of 31 10k resistors are needed, and according to the design rules they mush be at least 5.65 microns away from each other. Candence does not give you the exact positions of the resistors rather the center point, so in order to make all of the resistors on the grid and spaced correctly the center points were spaced by 10.65 microns in the y direction, and were placed at -2.85 in the x direction. After laying out all of the resistors correctly the metal layers needed to be connected by clicking on the metal layer in the layout view and drawing a rectangle connecting the end of one to the start of another. By connecting the end of one metal to the start of two others you make the following two in parallel, where as connecting the end of of to the start of another puts those two in series. After connecting the metals in the correct way pins were placed on every input pin B0-B9, one for ground, and one for Vout. Ground is a special case in that it needs to be labeled gnd! with the exclamatoin mark to indicate the global value ground in cadence.
Image 3: Layout view of 10-bit DAC using 31 10k resistors.
After making the layout the DRC function was used to ensure no errors were found with the layout, followed by extracting the layout so the the LVS could be used. After running the LVS command, the output file from the LVS file can be opened to verify that the schematic netlist matches the extracted layout netlist.
Image 4: DRC completition, verifying that zero design rules have been broken.
