Lab 2 - ECE 421L
Author: Nicholas Mingura,
Email: mingura@unlv.nevada.edu
09/12/2018
Prelab:
The
first step to the lab was to download the files that were given to us
in the lab instructions, unzip them and then add them to the cmos
files. This download was the schematics and cellviews for the examples
and problems needed to finish the lab.
Image 1: File path in Library manager for prelab schematic.
As
seen above, after completing the first steps I navigated through the
library manager to the schematic that was needed to simulate. After in
the schematic the Vin was changed to 12m V to change the amount of
steps in the simulation to a noticable degree.
Image 2: Schematic of prelab circuit with Vin changed to 12m V.
Image 3: Simulation of the prelab circuit showing a differnt amount of steps taken by Vout in the graph.
1LSB = Vdd/2^n
= 5/2^10
= 4.883mV
Lab:
For
this lab the goal was to create our own 10-bit digital to analog
converters and replace the prexisting symbos schematic with out our
own. The first step to make a new schematic using resistors to make the
DAC.
Image 4: 10-bit DAC schematic
This
kind of DAC resistance at Vout will be R as long all resistors are the
same value and is shown in the following hand calculations with a 5-bit
DAC
Image 5: Hand calculations showing resistance at Vout is R or in this case 10k ohms.
After
creating the schematic the Ideal_10bit_DAC was copied but had the
schematic replaced witht the above schematic.
Image 6: Library manager showing
After
replacing the schematic the sim_Idal_ADC_DAC was opened and the
preexisting DAC was replaced with the newly created one and simulated
to show that it still is working.
Image 7: Schematic with newly created DAC
Image 8: Simulation of newly created DAC
This
graph has a few weird steps in the middle at higher and very low
voltages and had to have simulation settings changed to make the full
simulation run, however this causes some degrading accuracy in the
graph. To further insure accuracy more tests were simulated one were
the DAC was feeding a capacitor of 10pF, another of it feeding a 10k
resistor, and another feeding the resistor and the capacitor.
Image 9: Resistor fed by DAC schematic
Image 10: Resistor fed by DAC simulation
Image 11: Capacitor fed by DAC schematic
Image 12: Capacitor fed by DAC simulation
Image 13: Capacitor and Resistor fed by DAC schematic
Image 14: Resistor and capacitor fed by DAC schematic
If
the switches in the DAC circuit are not significatly samller in value
than the resistors this will cause the overall resistance to be higher,
in turn making the output voltage lower.
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