Lab 5 - EE 421L

Francisco Mata Carlos

email: matacarl@unlv.nevada.edu

10/10/18

Pre_lab:

Lab description:

The goal of this lab is to design, layout and simulate two CMOS inverters. One inverter is using 12u/.6u for the PMOS and 6u/.6u for the NMOS, and for the second inverter, 48u/24u where the devices use a multiplier, M = 4. 

Below are the schematic and symbol for 12u/6u inverter

Below are the layout, extracted, DRC, and LVS for the 12u/6u inveter

Below are the schematic and symbol for 48u/24u inverter

Below are the layout, extracted, DRC, and LVS for the 48u/24u inveter

Below are the schematic and simulations for the 12u/6u inveter using Spectre

Below are simulations for the 12u/6u inveter using UltraSim

Below are the schematic and simulations for the 48u/24u inveter using Spectre

The simulations above show that by increasing the capacitor value, the RC time increases, which causes the output voltage not to be completely inverted as the input switches from 0V to 5V within the time given, or the pulse period.