Lab 1- EE 421L
Layout and simulation of a resistive voltage divider
Lab Description:
I will demonstrate the use of Cadence and set it up for use with ON's C5 process using the MOSIS scalable CMOS (SCMOS) design rules. As well as simply showing some of the images in this tutorial with some simple coherent narrative, and discussing how regular backups will be used throughout.
Prelab:
Request CMOSedu account, from Dr. Baker, prior to first class and review materials found here.
Lab:
1. Getting into Cadence and setting up to create Tutorial_1 library
Adding Tutorial_1 into the cds.lib file through the default text editor
2. Preparing to draw circuit by creating R_div
3. I put two 10K resistors, ground and a DC voltage source as seen below. Labeling the input and output voltages, 'Vin' & 'Vout'.
4. Once the schematic is done launch ADE L, transient for 1 second. With 'Vin' and 'Vout' to be plotted.
Before running, I saved the state, 'spectre_state1' and then pressed the green run button.
Finally I backed it up again to make sure they are safe in multiple places.
