Lab 7- EE 421L
Using buses and arrays in the design of word inverters, muxes, and high–speed adders
Authored
by Victor Martinez
martiv6@unlv.nevada.edu
November 3, 2018
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Tutorial 5 seen here.
- Read through the entire lab before starting it.
Lab
description:
Schematic for 4 bit inverter
| Schematic | Symbol |
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| Simulation of 4-bit Inverter | 4-bit inverter Plot |
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Schematics and Symbols for 8-bit: AND, inverter, NAND, NOR and OR
| AND Schematic | AND Symbol |
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| Inverter Schematic | Inverter Symbol |
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| NAND Schematic | NAND Symbol |
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| NOR Schematic | NOR Symbol |
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| OR Schematic | OR Symbol |
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| 8-bit Gates Schematic | 8-bit Gates Plots |
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| 2-to-1 MUX Schematic | 2-to-1 Mux Symbol |
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The
2-to-1 MUX output is defined as Z=A*S + B*Si and its inputs are A, B,
S, and Si. It allows one of the two inputs to be passed to Z when
selected by S. If the input at A is to be passed to Z then we set
1 to S and 0 to Si.| 2-to-1 MUX Schematic | 2-to-1 MUX Schematic Plot |
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| 2-to-1 DEMUX Schematic | 2-to-1 DEMUX Plots |
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The
2-to-1 DEMUX output is defined as Z*S =A and Z*Si=B. It
allows one input to be passed to two outputs A and B when selected by
S. If the input to Z is to be passed to A then we set 1 to S and
0 to Si.| 8-bit 2-to-1 DEMUX/MUX Schematic | 8-bit 2-to-1 DEMUX/MUX Symbol |
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| Simulate 8-bit 2-to-1 DEMUX/MUX | 8-bit 2-to-1 DEMUX/MUX Plot |
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Full Adder Schematics and Layout
| Full Adder Schematic | Full Adder Symbol |
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| 8-bit Full Adder Schematic | 8-bit Full Adder Symbol |
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| Simulate 8-bit Full Adder | 8-bit Full Adder Plots |
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| Full Adder Layout | Full Adder DRC |
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| Full Adder LVS | Full Adder Extracted |
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| 8-bit Full Adder Layout | 8-bit Full Adder DRC |
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| 8-bit Full Adder LVS | 8-bit Full Adder Extracted |
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Backing up Work
Zipping up lab work and uploading on google drive
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