Lab 5- EE 421L
Design, layout, and simulation of a CMOS inverter
Authored
by Victor Martinez
martiv6@unlv.nevada.edu
September 29, 2018
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Tutorial 3 seen here.
Lab
description:
- Draft schematics, layouts, and symbols for two inverters having sizes of:
- 12u/6u
- 48u/24u where the devices use a multiplier
Schematic, Layout and Symbol (12u/6u)
Schematic, Layout and Symbol (48u/12u)
- Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
12u/6u ( Schematic, Spectre, UltraSim)
- Use UltraSim and repeat the above simulations
48u/24u (Schematic, Spectre, UltraSim)
Backing up Work
Zipping up lab work and uploading on google drive
Lab Files lab5_vm.zip
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