Lab 4 - EE 421L 

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Authored by Victor Martinez

martiv6@unlv.nevada.edu

September 23, 2018

Lab description: This lab will have several NMOS and PMOS simulations, and to create layouts with probe pads.

Pre-lab work:

• Back-up all of your work from the lab and the course.  
• Read through this lab before starting it.
  
• Go through Tutorial 2 seen here. 
• In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V.  

Lab:

            ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. 

Using a 6u/600n width-to-length ratio

            ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. 

Using a 6u/600n width-to-length ratio

            ID v. VSD (note VSD not VDS) of a PMOS device for VSG varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 

5 V in 1 mV steps. Using a 12u/600n width-to-length ratio.

            ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. 

Using a 12u/600n width-to-length ratio.  

            Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads

Layout                                                                                   Extracted

Schematic                                                                          Symbol

DRC and LVS

Layout with pads

Extracted

DRC and LVS of NMOS with Pads

            Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads

Layout                                                                Extracted

PMOS with Pads

DRC and LVS of PMOS with pads

Backing up Work

    Zipping up work and putting into google drive

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