Lab 3 - EE 421L 

Victor Martinez

September 19, 2018

Layout of a 10-bit digital-to-analog converter (DAC) 

Prelab:

• Back-up all of your previous work from the lab and the course.
• Finish Tutorial 1 seen here.

Lab:

• Use the n-well to layout a 10k resistor as discussed in Tutorial 1 
• Use this n-well resistor in the layout of your DAC
• Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked)
• All input and output Pins should be on metal 1
• DRC and LVS, with the extracted layout, your design (show the results in your lab report)
• Zip up your final design directory and place it in the lab3 directory, with a link on your lab report, so the grader can examine both the layout and schematic (and simulations)

Layout of 10k resistor

    Looking at the parameters of the C5 process, the sheet resistance is 796 ohms/square

our minimum legnth will be 3.6 um

using the equation above and using 10k as our resistor value, plugging the values in gets us our length to be 45.3 um after accounting for it being disivible by lambda.

Layout of DAC Using 10k N-Well Resistor

After seperating the resistors by 5.4 um which is the minimum distance to not violate any of the C5 proccess I began to stack them with equal distance between them.

After putting all 31 one of them down and wiring them I DRC it and then ran an LVS with the schematic from lab 2 and got it to match .

I plugged in the layout to the schematic from lab 2 and it got simliar values like before.

with the layout i created it gave a simliar step ladder shape to the output.

zip for layout and stuff here

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