- Finish Tutorial 1
First is to create a a new cell within the Tutorial 1 Library called "R_div" this will be in the schematic view.
After creating the voltage divider, it is imperative to "check and save" the file on the top left of the Schematic Editor. Above we can see in the log that the schematic check has completed with no erros and the schematic has been saved.
Next is to simulate the schematic that has been created as R_div. First is to open the Virtuoso Analog Design Environment (ADE) by clicking on Launch->ADE L. Then once ADE opens, next is to press Setup->Simulator/Directory/Host and ensure that "spectre" has been chosen by default in the Simulator drop down menu.
After simulation this should be the desired output of the Voltage Divider. With Vout approximately half of Vin. This simulation was created by pressing on Analyses->Choose and then selecting "tran", entering stop time "1", and checking the "enabled" box. Before simulating, be sure to save the state in cellview for access to the simulation again at a later date.
The next step is to create a symbol of the schematic above. To create the schematic above, I removed the voltage source and the bottom connecting wires and added pins to the input and the output (bindkey P or Create->Pin). After doing so, I checked and saved to ensure that schematic is thoroughly correct.
Next I created a symbol of the R_div schematic by selecting Create->Cellview->From CellView and then hit OK twice. Once that has been done, the symbol appears like the image above.
Then I deleted the other lines that were not "Vin" or "Vout" and created a symbol that resembled the voltage divider schematic. I used Create->Shape->Line to make it look like resistors were connected. Once that was done, I checked sand saved to ensure no errors occured.
Next is to create a layout called R_n_well_10k. For the 10k resistor.
10k/800 Ohms = 12.5 or approx 12 lambda.
if we use a width of 4.5 um then then length would be approx 56 um. I used 56.1 to ensure that it would fit on the grid. (within 0.15) If it did not fit, the DRC check would give 4 errors since it does not fit on the grid. After this, the metal1 connections are added to both sides of the n-well and the res_id layer is added on to the original rectangle (4.5 um x 56.1 um)
After creating the 10k N-Well Layout, I then extracted the layout (Verify->Extract) and then opened that file within the Library Manager to ensure that the output is approximately 10k.
Above is the layout for R_div, I instantiated the 10k resistor layouts and connected them using the metal1 drw layer. Then I verified the DRC to ensure there were no errors. Originially I had an error due to too small of a spacing between the two resistors.
After adding the metal1 layer pins to the input, output, and gnd the next step would be to first DRC the layout to ensure there are no erros (Verify->DRC). Then to extract the layout (Verify->Extract). Then to finally LVS the extracted layout and the schematic (Verify->LVS), once doing so the output above should be the desired results. The net-lists match.
