Lab 7 - EE 421L
11/7/18
Pre-Lab:
- Back-up
all work from the lab and the course
- Go
through Cadence Tutorial 5
- Read
through the lab before starting to work on it
- This
lab focuses on using buses and arrays in the design of word inverters, muxes, and high-speed adders
- Schematic
- Symbol
- Create an equivalent, more concise schematic of a 4-bit word
inverter using arrays and buses, then create a symbol
- Schematic
= 
- Symbol
- Simulation schematic using the symbol for a 4-bit word
inverter
- Simulation results of the 4-bit word inverter
- Create schematics and symbols for an 8-bit input/output array
of: inverter, NAND, NOR, AND, and OR gates. Provide simulation examples
using these gates
- Inverter:
- Schematic (8-bit)
- Symbol:
- NAND:
- Schematic (1-bit)
- Schematic(8-bit)
- Symbol
- NOR:
- Schematic (1-bit)
- Schematic (8-bit)
- Symbol
- AND:
- Schematic (1-bit)
- Schematic (8-bit)
- Symbol
- OR:
- Schematic (1-bit)
- Schematic (8-bit)
- Symbol
o Schematic to simulate the 8-bit NAND, NOR, AND, inverter, and
OR gates
o Simulation results of the 8-bit NAND, NOR, AND, inverter,
and OR gates
The bits
used to perform the operation for gates NAND, AND, NOR, and OR are 1010 and
0011.
- Create schematics and symbols for an 8-bit input/output array
of a MUX/DEMUX and simulate.
- MUX/DEMUX:
- Schematic
(1-bit)
- Symbol
- Schematic with inverter (1-bit)
- Symbol
- Schematic with inverter (8-bit)
- Symbol
§ Schematic to simulate the 1-bit 2:1 MUX
§ Simulation results of the 1-bit 2:1 MUX
The 2:1
MUX acts as a 2 to 1 switch with S being the selector. When S is high (1), the
output should be A and when S is inverted [low (0) à Si is high (1)], the
output should be B.
§ Schematic to simulate the 1-bit 2:1 DEMUX
§ Simulation results of the 1-bit 2:1 DEMUX
The
input is now Z; the data from Z will be fed to either A or B depending on
whether the selector (S) is on or off. When selector is on, the data from Z will
go to A, and if the selector is off, the data from Z will go to B; however, on
the simulation result, at the transition point of the selector (from on to off
or off to on), A/B takes an arbitrary value because at that switching point,
the selector is not exactly on nor off.
§ Schematic to simulate the 8-bit 2:1 MUX
§ Simulation results of the 8-bit 2:1 MUX
When S is on, the output on Z should be A and
when S is off, the output on Z should be B.
- Create schematics and symbols for an 8-bit input/output array
of a FULL ADDER and simulate; then, create a layout. Provide proof of DRC
and LVS.
- FULL ADDER:
- Schematic
(1-bit)
- Schematic
(8-bit)
- Symbol
§ Schematic to simulate the 1-bit FULL ADDER
§ Simulation result of the 1-bit 2:1 FULL ADDER
The
result is obtained by adding A 10101010 and B 11001100
§ Schematic to simulate the 8-bit FULL ADDER
§ Simulation result of the 8-bit 2:1 FULL ADDER
The
result is obtained by adding A 00001111 and B 11110000
- Layout
- Extracted
- DRC
- LVS
- The cells used to generate the images used on this webpage can
be downloaded in Lab7_hie
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