Lab 6 - ECE 421L
Authored
by Jovanne Dahan
dahanj1@unlv.nevada.edu
October 23,
2018
Post-lab:
·
2-Input NAND Gate
Both the schematic and symbol for the NAND gate was already finished
beforehand as a result of completing Tutorial
4. The only addition I made was embedding my initials on the symbol.
For the layout, instead of making a 12u/.6u PMOS, I used a 6u/.6u PMOS.
The rest of the layout stayed as it was from the tutorial.
After completing the layout I LVS’d the
extracted view with the schematic view and the net-list matched.
·
2-Input XOR Gate
The schematic for the XOR gate was the simplest part of the design because
it was already given on the Lab 6
webpage. I did not have any difficulty with the symbol either.
The layout took a few tries to DRC and it was the most difficult layout I
have done until the Full Adder later. The two inverters to make Ai and Bi was simple
but the rest if the XOR gate required more thinking. The reason being I had to
figure out where A, B, Ai, and Bi would connect to the PMOSes
and NMOSes.
The biggest impediment to the design of the XOR gate was the fact that I
did not realize I had to stretch the N-well so that it would touch the body of
the PMOS. I spent about an hour looking at my layout until I realized that
important rule. After I took care of that, it LVS’d
fine as can be seen below.
·
NAND, XOR, and Inverter Simulations
Below is the schematic I used to test the operation of the logic gates.
The following waveform shows that they are working as intended. At the 200ns
mark on the waveform we can see that AxorB has a
steep drop followed immediately by a steep climb. This is because there is a
rise and fall time for the input pulse. If the rise and fall time are too long
then the gate would be inaccurate for that stretch of time.
·
Full Adder Schematic, Symbol, Simulations
The schematic and symbol were already given in the Lab 6 webpage; therefore,
there is nothing more to elaborate on.
Below is the circuit I used for the simulation of my Full Adder. At first
I forgot to add the net Vdd and the output waveforms
were not pretty. Again the outputs are showing signs of glitches at the 200ns,
400ns, and 600ns marks.
·
Full Adder Layout and LVS
My layout for the Full Adder is a mess. To start, I instantiated 3 NAND
gates and 2 XOR gates. I then arranged them in a similar order to the schematic
view of the Full Adder: that is, NAND-XOR-NAND-XOR-NAND. Following that step, I
decided to flatten all of the gates because they all possessed vestigial parts
that was no longer needed for the Full Adder (i.e. the pins). I then connected
the gates using the schematic as a reference. This process required using the
poly-metal1 to make bridges over the polys (because the polys would block the
path for another poly wire). It required more tries than the layout for XOR
gate to complete because of its complexity.
It also took me many tries to successfully LVS the extracted view. I made
a lot of small mistakes during the layout process of the design that the DRC
did not consider a breach of the rules. Consequently, when it came to LVSing the design, the net-lists would not match even
though the layout DRCd just fine. After carefully
looking though the output report of the LVS, I managed to find all of the error
in my layout. The LVS below shows that the net-lists for the schematic and the
extracted view matched.
