Lab 5 - ECE 421L 

Authored by Jovanne Dahan

dahanj1@unlv.nevada.edu

9 October 2018

 

Post-lab:

 

·        12u/6u Inverter

 

The first step I undertook in creating the inverter was to draw the given schematic. After checking and saving, I created a symbol view for the circuit and drew the symbol for an inverter; connecting the input to A and output to Ai. Moving on to the layout part of the design process, I simply followed the same steps I took in Tutorial 3 for creating the layout of an inverter. After DRCing showed no errors, I moved on to the last step: LVSing the extracted view with the schematic. Seen below is the results of the LVS and the schematic view of my 12u/6u inverter.

inv1_extractedinv1_schem

 

inv1_LVS

 

 

·        48u/24u Inverter

 

The steps to create a 48u/24u inverter was the same as the 12u/6u inverter except for the fact that the multiplier had to be set to 4 for the NMOS and the PMOS in the schematic view. Similarly, when laying out the circuit a multiplier of 4 had to be used for the PMOS and the NMOS cells.

inv4_extractedinv4_schem

 

inv4_LVS

 

 

·        Spectre simulations for 12u/6u inverter

 

Directly below is the schematic for testing my 12u/6u inverter. As the lab instruction directed, I simulated the schematic four times using spectre with values of C ranging from 100fF, 1pF, 10pF, to 100pF. The waveforms for each capacitor values are below in the respective order (left to right, top to bottom).

inv1_s1

 

At 100fF, the inverter works as intended: inverting the value of the input from logic value “1” to “0” or vice versa. Increasing the capacitance increases the amount of time it takes to charge/discharge the capacitor resulting in the following waveforms.

inv1_spectre1inv1_spectre2

 

inv1_spectre3inv1_spectre4

 

 

·        Spectre simulations for 42u/24u inverter

 

I took the same steps to simulate this circuit as with the previous. I did a transient analysis from 0 to 20ns with the pulse being 5V.

inv4_s1

 

Similar to the 12u/6u inverter, the increase in capacitance makes the charge time longer. However, the waveforms below are showing a less drastic change. This might be due to the fact that the resistivity between drain and source have decreased due to the larger area of the PMOS.

inv4_spectre1 inv4_spectre2

 

inv4_spectre3inv4_spectre4

 

 

·        UltraSim simulations for 12u/6u inverter

 

Simulating with UltraSim showed no noticeable difference from the waveforms generated with Spectre. The simulation speed for UltraSim also did not feel any faster than Spectre.

inv1_s1

 

inv1_Ultra1 inv1_Ultra2

 

 

inv1_Ultra3 inv1_Ultra4

 

 

·        UltraSim simulations for 42u/24u inverter

 

Since the circuits I have simulated are quite small, the simulation speed and accuracy difference from UltraSim and Spectre are miniscule.

inv4_s1

 

inv4_Ultra1 inv4_Ultra2

 

inv4_Ultra3 inv4_Ultra4

 

My cells for the content above: lab5.zip

 

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