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Lab 1: Laboratory Introduction - EE 421L Author: Mario Verduzco Email: Verdum1@unlv.nevada.edu 09/04/17
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Pre-lab:
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Lab description:
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Experimental Results:
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· The lab reports will be drafted using html and placed on CMOSedu. · Prior to the first day of lab, but no earlier than one week before the lab starts, get a CMOSedu account, using your UNLV email address, from Dr. Baker, rjacobbaker@gmail.com · Review the material seen here covering editing webpages (do this before the first lab) |
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The objective of this lab is to properly setup Cadence Virtuoso and have a proper understanding on how to create and submit HTML lab reports. |
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Experiment #1 - Follow and complete Cadence tutorial 1 from CMOSedu. The tutorial consists of setting up ON’s C5 process for use in the lab. After downloading, uploading and defining the cds.lib we were able to create a resistive voltage divider schematic for simulation. |
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The other CMOSedu tutorials were followed in order to plot the schematic on a white background. |
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Resistive Voltage Divider |
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Resistive Voltage Divider Tran Simulation |
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Using the ADE - L we were able to simulate the resistive voltage divider using a transient simulation. |
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Lastly, it is important to do regular backups in order to have your hard work saved. I will be using google drive and uploading the zipped file of the lab report and figures as my back up method. |
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Zipped lab file |
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Google drive uploaded file |