Lab 07 - EE 421L 

Authored :: Aaron Escobedo

Email :: Escoba3@UNLV.Nevada.edu 

Due :: November 8th, 2017

Lab description

This lab will familiarize ourselves with the design using busses, arrays, word inverters, muxes, and high-speed adders.. 

Prelab

We will begin our lab by completing the tutorial 5 set up on the cmosedu.com website; below is now some of my completed work. 

Initially, we want to place 31 inverters in series to create a ring oscillator 

Since this can be inconvient to have within the circuit, we can simplify it by creating a bus of wires such as show below.

This is now much easier to work with - however should should still simulation it to ensure it works in the same manner as our previous schematic.

Initial ring oscillator schematic

2nd circuit with simplified ring oscillator

We can clearly see, they produce the same results, however, one is much easier to place in a large circuit. 

From here, we should try to create a layout for these circuits - which can lead us to learn a few new tricks. 

First, open up an inverter, copy it, and place it next to the first one

Next, lets add metal1 inbetween the vdd!, gnd!, and A pins, and then delate the other inverter

Now, we can copy it as many times as we want - for us, lets select the columns to be 30 to create a row of  31 inverters next to each other.

We should now see something like this



DRC the layout




We should now extract and LVS this circuit to ensure we created it properly and simulation this new circuit.


We are looking good

Now, lets create a generic symbol for our circuit and simulation once more to simplify it even further.

Initial schematic

Created symbol

Simulation schematic

Results

This all ends up being the same as our orginal concept but now much simpler! This concludes out tutorial 5 Prelab.

6/0.6 Inverter Schematic

Associated Symbol

Now we will create a sample 4-bit inverter using this 6/0.6 inverter; this is shown below


Orginal concept


Simplified

Now lets create a new symbol;

New symbol

With the new symbol, we can simulate it - as was expected of us, I set up the outputs to be placed with various capacitors to see the response of this circuit.

Here are some of the outputs

General outputs - we can see the delay difference between each node due to capacitors

Zoomed in - we can see at Out<3>, it reached 1 time constants, while Out<2> and Out<1> are much slower

Now that we are familar with this process, we can do something similar to create an 8-bit version for an Inverter, NAND, AND, OR, XOR and NOR logic gates

Logic	Initial Schematic	Symbol	Simulation schematic	Results
8 bit NAND
8 bit AND
8 bit NOR
8 bit OR
8 bit XOR

From here, we are next asked to create a 2-to-1 demux/mux as well as an 8-bit version of the same schematic; here are the results of that

Logic	Initial Schematic	Symbol	Simulation schematic	Results
2-to-1 MUX
8 bit 2-to-1 MUX

We can sere by looking at the schematic the functions of this circuit. We receive two inputs, A and B. but only 1 output. Which output is selected is determined by the logic of the S or Si input. If S is high, than the output is A, if Si is high (S is low) then the output is B. This defines a 2-to-1 MUX.

Finally, we were asked to create a full adder and an 8-bit version of a full adder - this is now shown below. 

Logic	Initial Schematic	Symbol	Simulation schematic	Results
full adder

Here is my work backed up with a link to download and simulate all of these files

Link to backed up work

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