Lab Project - ECE 421L
I created this symbol for it.
I tested the symbol with this simulation circuit and plotted the outputs.
A parity checker can be used for error detection when transmitting data. For an even parity checker, the parity bit will make the total numbers of ones in the data an even number, ie. if the total number of ones in the data is odd, parity bit will be a 1 making the total number even.
From top to bottom of V1, the bits read 00011000 0 1 with the first 8 bits being data and the last two bits being the parity bit and the checking bit, respectively. Here the data bits have a total of 2 ones, an even number, so the parity bit should be 0. The parity bit is 0 and the checking bit shows a 1 meaning it is valid, as it should
V2 reads 11001111 1 0. There are 6 data bits, an even number, so the parity bit should be 0. Parity bit is 1 so the check fails and the checking bit shows 0 meaning invalid.
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Part 2:
I reconsidered my original parity circuit and decided I could save space by combining the last XOR gate and inverter to create an XNOR gate. I also added the digital output pad that was given on the bottom of the Cadence tutorial page here.
I simulated this again to make sure the parity checker was still operational, and I got the same output as I did in part 1.
The XOR gate schematic I used was:
I decided to redo my original layout of the XOR from lab 6 to show the improvements I have made with my layouts. Here is the before and after XOR gate layouts.
I then had to created a layout for the XNOR gate. I used this schematic:
Noticing
this is nearly equivalent to the XOR gate, the only change I had to
make was swapping A and Ai in the XOR layout. My newly designed layout
made this easy.
Here is the XOR and XNOR layout side-by-side to compare:
I then laid out the gates to match the schematic above.
I connected the digital output pad given to me and extracted the layout.
My layout passes DRC and LVS tests.
All project files can by accessed in the proj.zip folder here.