Detector Project - Fall 2016 - EE 421L 

Authored by Staford Snow, snows4@unlv.nevada.edu

11/16/2016

  

CLICK HERE TO JUMP TO PART 2


Project Description:

For my project, I am creating a sequence detection circuit.  The circuit takes a serial input and outputs high when the sequence 101011 is detected.  There are several components that are used in the design of the detection circuit.


To begin, I created a schematic and symbol for an inverter.  This inverter is used several times in the circuit.

 

12u_6u_m1_inverter_sds_f16_schematic.png  12u_6u_m1_inverter_sds_f16_symbol.png

 

Next I created a schematic and symbol for a transmission gate.  The transmission gate is used in the creation of the D flip-flops, but I will get to them shortly.

 

12u_6u_m1_tg_sds_f16_schematic.png  12u_6u_m1_tg_sds_f16_symbol.png

 

With the necessary "building blocks" for the D flip-flop, I drafted a schematic and symbol to be used in the detection circuit.

 

d_ff_sds_f16_schematic.png

 

d_ff_sds_f16_symbol.png

 

I verified the correct operation with a simulation circuit and graphical output.

 


sim_d_ff_sds_f16_schematic.png

 

sim_d_ff_sds_f16_graph.png

 

With the D flip-flop complete, I designed the schematic and symbol for a 6-input NAND gate.

 

12u_6u_6in_nand_sds_f16_schematic.png

 

12u_6u_6in_nand_sds_f16_symbol.png

 

For the next part of the circuit, the SR latch, I needed to create a 2-input NAND gate.  I drafted the schematic and symbol for the design.

 

12u_6u_2in_nand_sds_f16_schematic.png  12u_6u_2in_nand_sds_f16_symbol.png

 

The last part needed for the detection circuit was an SR latch.  This is used to hold the output high when the circuit detects the sequence.  I drafted the schematic and symbol.

 

sr_latch_sds_f16_schematic.png

 

sr_latch_sds_f16_symbol.png

 

I put together a simulation circuit and verified the latch worked correctly by viewing the graphical output.

 

sim_sr_latch_sds_f16_schematic.png

 

sim_sr_latch_sds_f16_graph.png

 

With the pieces complete, I combined everything into the detector circuit and created a symbol.  One thing to note: since the input is read serially, the the D flip-flops on the bottom hold the desired sequence (101011) from right to left.

 

detector_sds_f16_schematic.png

 

detector_sds_f16_symbol.png

 

I put together a circuit to simulate the detection circuit and saw it was working correctly by viewing the output waveform.

 

sim_detector_sds_f16_schematic.png

 

sim_detector_sds_f16_graph.png


This concluded phase 1 of my detection circuit!  I have included a zipped version of this project, so far, here.

 


 

Welcome to part 2 of my final lab project!

 

For the second part of the lab project, I created a verified layout of the design I created in part 1.  I also added additional functionality to turn "off" the detect signal with the input of a different sequence, 100110.  The serial input is read sequentially by both the "on" and "off" portions of the circuit.


To enable the turning "off" the detect signal, I implemented a series of D flip-flops connected to a 6-input NAND gate similar to the initial design.  This NAND gate connects to the Reset input of the NAND gate.  I added this to the original schematic.

 

part_2/detector_sds_f16_schematic_v2.png

 

I also updated the symbol accordingly.

 

part_2/detector_sds_f16_symbol_v2.png

 

I inserted this new schematic into my simulation to verify operation.  Upon viewing the graphical output, I saw it worked!

 

part_2/sim_detector_sds_f16_graph_v2.png

 

I then began laying out the components for the complete detect circuit.

 

I started with the inverter.  I verified the layout passed DRC and LVS.

 


part_2/12u_6u_m1_inverter_sds_f16_drc.png

 

part_2/12u_6u_m1_inverter_sds_f16_layout.png  part_2/12u_6u_m1_inverter_sds_f16_lvs.png

 

Next was laying out the transmission gate and verifying the design passed DRC and LVS.

 


part_2/12u_6u_m1_tg_sds_f16_drc.png

 


part_2/12u_6u_m1_tg_sds_f16_layout.png  part_2/12u_6u_m1_tg_sds_f16_lvs.png

 

Following the successful layout of the transmission gate, I designed the layout for the D flip-flop and verified the passing of DRC and LVS.

 


part_2/d_ff_sds_f16_drc.png

 


part_2/d_ff_sds_f16_layout.png  part_2/d_ff_sds_f16_lvs.png

 

The 6-input NAND gate was the next device I created a layout for.  I again verified it passed DRC and LVS.

 


part_2/12u_6u_6in_nand_sds_f16_drc.png

 

part_2/12U_6u_6in_nand_sds_f16_layout.png  part_2/12u_6u_6in_nand_sds_f16_lvs.png

 

Before drafting the layout of the SR latch, I put together the 2-input NAND gate.  It also passed DRC and LVS.

 


part_2/12u_6u_2in_nand_sds_f16_drc.png

 


part_2/12U_6u_2in_nand_sds_f16_layout.png  part_2/12u_6u_2in_nand_sds_f16_lvs.png

 

Finally, I drafted the layout for the SR latch.  I verified my layout passed DRC and LVS.

 


part_2/sr_latch_sds_f16_drc.png

 

part_2/sr_latch_sds_f16_layout.png  part_2/sr_latch_sds_f16_lvs.png

 

I then compiled these pieces into a layout of the revised detector circuit.  This passed DRC and LVS as well.

 


part_2/detector_sds_f16_drc.png

 

part_2/detector_sds_f16_lvs.png

 


part_2/detector_sds_f16_layout.png

 

Close-ups of the layout are below:

 


part_2/detector_sds_f16_layout2.png

 


part_2/detector_sds_f16_layout3.png

 

 

This concludes the detect circuit project!  I have a zipped version of the completed project here!

 


 

 

 

 

Return to my labs

Return to EE421L