Lab 7 - ECE 421L
Prelab:
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Tutorial 5 seen here.
- Read
through the entire lab before starting it.
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Lab:
In this lab we learned how to
create logic gates. Not only did we create AND, NAND, OR, and NOR gates, but we
had to make them all 8-bits.
First we must construct the
schematics for all gates and then from there we can create symbols that will
later be simulated and turned into 8-bit input/outputs.
Using the NAND that we created
earlier this semester in lab, we instantiate it into our schematic and turn it
into an 8-bit NAND adding the fat wires to the ends. Below is the schematic and
symbol for the 8-bit NAND.
Figure 1
Figure 2
We do the same for the AND gate
now. For the AND gate we can construct a schematic using the NAND gate and
putting an inverter in front of it. Below is the schematic and symbol for the
8-bit AND.
Figure 3
Figure 4
Next we construct our NOR
schematic and transform it into an 8-bit NOR. Below is the schematic and symbol
for the 8-bit NOR.
Figure 5
Figure 6
To construct the OR gate we can
use the same process as we did for the NAND. We take our NOR and put an
inverter infront of it to make an OR gate. . Below is
the schematic and symbol for the 8-bit OR.
Figure 7
Figure 8
Now that all the 8-bit gates are
constructed and ready to go, we can put them together and simulate them to
check if they work. As seen below, the simulation is successful and all gates
perform exactly how they’re supposed to.
Figure 9
Figure 10
Next part of the lab is to
construct an 8-bit 2-1 Mux/DeMux. Below we see the
basic schematic for the Mux/DeMux. When building the
schematic it is noticeable that the S and Si can be
Plotted as one since they are compliments of
each other. Because of this we combine S and Si to make one variable which has
an inverter connected to it.
Figure 11
Figure 12
Now we can use our 8-bit Mux/DeMux to simulate it and check its performance.
Figure 13
Figure 14
Now we can make our 8-bit Mux/DeMux. Below you can observe the symbol for the 8-bit Mux/DeMux along with the test schematic and the successful
simulation.
Figure 15
f
Figure 16
Figure 17
Final part of this lab was to
construct a schematic for an 8-bit Full Adder and also create a layout with
successful DRC and LVS.
To begin we start creating the
schematic for the Full Adder.
Figure 18
From the schematic we derive a
symbol that will later on assist in creating our 8-bit Full Adder. With the
symbol we test it to make sure that it works and the outputs are exactly what
we want. As it can be seen, the simulation was successful ensuring that the
Full adder schematic was built correctly.
Figure 19
Figure 20
From that we now lay out the
1-bit Full Adder. From the layout we derive our extracted view along with
successful DRC and LVS.
Figure 21
Figure 22
Figure 23
Figure 24
Now that we have ensured that the
Full Adder schematic works and laid out the 1-bit Full Adder, we can create an
8-bit Full adder through the same steps.
Figure 25
Let us test the 8-bit Full Adder
before we move on to the layout to ensure that it works properly. It can be
seen below that the simulation does work as expected.
Figure 26
Now we can construct the layout.
For the layout we can instantiate our 1-bit Full Adder 8 times and connect the
needed outputs and inputs together.
Figure 27
Here is a closer look of the
8-bit Full Adder
Figure 28
Figure 29
Extract the layout and LVS to
ensure that our layout is right and matches our schematic we created.
Figure 30
Figure 31