Lab 5 - ECE 421L

 

 

Authored by Raheel Sadiq,

sadiqr@unlv.nevada.edu

October 5th, 2016

 

 

 

 

Prelab:

 

Pre-lab work

 

 

 

 

______________________________________________________________

Lab:

 

To begin this lab we start creating two CMOS inverters. The CMOS consists of thea PMOS and a NMOS. The size of the PMOS is 12u/0.6u and the size of the 6u/0.6u.

 

First we create the schematic for the CMOS. There is no dc voltage source. Instead we use a supply net.

 

schematic1m

Figure 1

 

Next we derive the symbol from the schematic

 

symbol12.6

Figure 2

 

 

Now that we have built the schematic, we can begin to create the layout for the CMOS. While making the layout we must pay attention to how we assign our pins. There should be a vdd, A, Ai, and gnd pin added to the layout to match the schematic pins.

 

layout1m 

Figure 3

 

We now extract our layout

 

exracted1m

Figure 4

 

 

After extraction we must DRC and LVS our design to confirm that there are no errors and that the netlists between the schematic and the extracted view.

 

DRC12.6

Figure 5

 

LVS12.6

Figure 6

 

 

After finishing our first CMOS, we begin to construct our second CMOS. The difference between this CMOS and the last one that was built is that this CMOS will have its PMOS and CMOS length and width multiplied by 4.

 

schematic4m

Figure 7

 

Next we derive the symbol from the schematic

 

symbol48.24

Figure 8

 

 

Now we can layout our design. The difference between this and the last CMOS will be the amount of fingers. There will be four fingers for the amount of multipliers we need. There still needs to be a vdd, A, Ai, and gnd pin added to the layout to match the schematic.

 

layout4m

Figure 9

 

Extracted view

 

Figure 10

 

 

DRC to make sure there was nothing wrong with the design and LVS to confirm the netlists between schematic and extracted view match.

 

DRC48.24

Figure 11

 

LVS48.24

Figure 12

 

 

After we have laid out our design and extracted our designs, we can now take the symbols and implement them into a circuit and simulate it with spectre and UltraSim.

The simulations are done with different values of capacitive loads. The loads that will be used are 100fF, 1pF, 10pF, and 100pF.

 

First we will be simulating our 12u/6u symbol.

 

100f

Figure 13

 

100fF load simulation:

Spectre

100f_Sim

 

UltraSim

Ultra_100f_Sim

 

 

1pF load simulation:

Spectre

1p_Sim

 

UltraSim

Ultra_1p_Sim

 

 

10pF load simulation

Spectre

10p_Sim

 

UltraSim

Ultra_10p_Sim

 

 

100pF load simulation:

Spectre

100p_Sim

 

UltraSim

Ultra_100p_Sim

 

 

Next we will be simulating our 4 multiplier symbol implemented in a schematic. The capacitive loads that will be used are 100fF, 1pF, 10pF, and 100pF.

 

 

4_100f 

Figure 14

 

 

100fF load simulation:

Spectre

4_1p_Sim

 

UltraSim

Ultra_4_100f_Sim

 

 

1pF load simulation:

Spectre

4_1p_Sim

 

UltraSim

Ultra_4_1p_Sim

 

 

10pF load simulation:

Spectre

4_10p_Sim

 

UltraSim

Ultra_4_10p_Sim

 

 

100kpF load simulation:

Spectre

4_100p_Sim

 

UltraSim

Ultra_4_100p_Sim

 

 

From all the simulations we can observe that spectre and UltraSim output similar results. The spectre state seems to be a little more accurate for analysis of a circuit over UltraSim.

 

 

lab5 folder

 

 

 

 

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