Lab 2 - EE 421L 

Authored by Sharyn Miyaji,

Email: miyajis@unlv.nevada.edu

Wednesday, September 14, 2016

Pre-Lab work:

First, download lab2.zip to your desktop to receive the files for Lab 2.  Then upload the lab2.zip into the CMOSedu folder on MobaXterm. Once the zip file is uplaoded, the type in the command unzip lab2.zip to unzip the file and then add DEFINE lab2 $HOME/CMOSedu/lab2 to the cds.lib file in the CMOSedu folder.  Open up Cadence by typing in virtuoso & and make sure to be in the CMOSedu directory.  The Library Manager should pop up when Cadence opens up and lab2 should be listed in the library.  If the Library Manager does not open, then click on the Tools tab in the Cadence commmand window.  Select lab2 library and open up the schematic of sim_Ideal_ADC_DAC, which is shown below.

An analog signal from the voltage source is being inputted into the 10-bit ADC, which converts an analog signal to a digital signal by breaking it down into 10-bits.  Those 10-bits then go through the DAC and creates an output analog signal, which is displayed above.  The results of the input and the output voltage are similar, but there are small errors in the output voltage simulation. The causes of those errors are the number of bits in the converters.  As seen in the equation below, N represents the number of bits in the converter and VDD is the voltage from the source.  LSB is the least significant bit, which is also the difference between the input voltage and the output voltage.  In the schematic, the VDD is 5 volts and the number of bits used in the DAC is 10 bits; therefore, the LSB is 4.88mV.

Lab work:

Next, my 10-bit DAC schematic is built using the symbol created above with an additional 10k resistor added to the bottom of the DAC.  Again, the schematic is converted into a symbol to make a simplified version of a DAC.
 
       

Below is the calculation of the output reisistance of the DAC by combining resistors that are in series and parallel, which result in the value of one resistor.
   

Delay, Driving a Load
   
To create a delay using a DAC, a 10 pF capacitor is added in parallel to the DAC with the B9 pin attached to a pulse source and the rest of the pins grounded as shown below.  As shown below, the pulse source being used is 0 to 5 volts, so the expected voltage at the time delay is 1.25 volts, which is a fourth of the input voltage.  A fourth of the voltage is expected because the ouput voltage is half of the input voltage and the time delay is at 50% of the output voltage.  To calculate the time delay, it is 0.7*R*C, where the reisistor is 10k and the capacitor is 10pF; therefore, the time delay is 70 ns.
   

 

schematic, delete the DAC, and replace it with the DAC that was created earlier as shown below.  The simulation should look like the one below the schematic.
   

 

Explain what happens if the DAC drives a 10k load. If the DAC drives a 10k load, it causes the output voltage to be half of the input voltage because the extra resistor creates an additional voltage divider.

Discuss what happens if the resistance of the switches isn't small compared to R.  If the resistance of the switches isn't small compared to R, it will cause the output voltage to be lower.  With the switch acting as a larger resistor, it will be in series with the other two resistors that are already implemented in the DAC; therefore, it increases the resistance value.

Back Ups

I will back up my files for this lab in my student drive and UNLV Google drive.