Lab 7 - EE 421L: Digital Integrated Circuit
Design Laboratory
Post-Lab:
Below are the post-lab deliverables.
Below in
figure 1 is the schematic for single gates and their perspective 8 input gates
in the following order: AND, NAND, NOR, OR, Inverter.
Figure 1
Below in
figure 2 is the schematic used to simulate the gates.
Figure 2
Below in
figure 3 is the simulation results of the above schematic. As you can see the 100fF load delays the
output of the gates.
Figure 3
Below in figure 4 is the schematic
views of the single bit, and 8 bit 2-1 MUX/DE MUX.
Figure 4
Below in figure 5 is the schematic used to simulate the operation of the 8
bit 2-1 MUX/DE MUX.
Figure 5
Below in figure 6 is the results of the simulation, as you can see if you
look at this as a 2-1 MUX the output(Z) is A when S(net4) is 5V or logic “1”,
and the output is B when S is 0V or logic “0”.
The DE MUX operation is just the reverse, when S is 1 Z’s input value
would go to A and when S is 0 Z’s input value woud go to B.
Figure6
Below in figure 7 is the schematic used to simulate the operation of the
DE MUX.
Figure 7
Below in figure 8 is the results of the simulation. **NOTE** when the DE MUX selector is
high(net4 = 5V) we do not care about the Value on B. When the selector is low 0V the output takes
the correct value.
Figure 8
Below in figure 9 is the schematic and the symbol of the Full Adder.
Figure 9
Below in figure 10 is the Layout and Extracted view of the Full Adder seen
above in figure 9.
Figure 10
Below in figure 11 is the successful LVS and DRC of the Full Adder.
Figure 11
Below in figure 12 is the 8 bit Full Adder schematic.
Figure 12
Below in figure 13 is close up view of the layout for the 8 bit Full
Adder. Notice the carry output of the
first adder is tied to the carry input of the second adder. This is repeated to
create the 8 bit Full Adder.
Figure 13
Below in figure 14 is the successful LVS and DRC of the 8 bit Full Adder.
Figure 14
Below in figure 15 is the schematic used to simulate the 8 bit Full Adder.
Figure 15
Below in figure 16 is the simulation results from figure 15 above.
Figure 16
Below is the truth table to verify operation of the 8 bit Full Adder. Note
that net4 is carry in and the table output refers to Co for Carry and
S<0> for Sum from the simulation results above in figure 16.
Full Adder Truth Table
Conclusion:
Lab 7 served to teach me how to properly use and label busses and arrays
for multiple input/output logic gates.
My Lab 7 files can be found here to authenticate unique individual experiments and designs.
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