Lab 5 - EE 421L: Digital Integrated Circuit
Design Laboratory
·
Back-up all of your work from the lab and the course.
·
Go through Tutorial 3
Post-Lab Scope
·
Draft schematics, layouts, and symbols for two inverters having
sizes of:
o 12u/6u (=
width of the PMOS / width of the NMOS with both devices having minimum lengths
of 0.6u)
o 48u/24u where
the devices use a multiplier, M = 4
·
Using SPICE simulate the operation of both of your inverters
showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
o Comment, in
your report, on the results
·
Use UltraSim (Cadence's fast SPICE simulator for larger circuits
at the cost of accuracy) and repeat the above simulations
Post-Lab:
Below are the post-lab deliverables.
Below in figure 1 you will see the schematic, layout, extracted and symbol
of the 12u/6u NMOS/PMOS respectivley.
Figure 1
Below in figure 2 you will see the LVS and DRC of the 12u/6u NMOS/PMOS
Figue 2
Below in figure 3 you will see the schematic, layout, extracted and symbol
of the 48u/24u NMOS/PMOS respectivley.
Figure 2
Below in figure 4 you will see the LVS and DRC of the 12u/6u NMOS/PMOS
Figure 4
Using
SPICE simulate the operation of both of your inverters showing each driving a
100 fF, 1 pF, 10 pF, and 100 pF capacitive load
- Comment, in
your report, on the results
Below in figure
5 you will see the Cadence simulation in the Spectre
environment of the single line inverter using the parametric sweep function and
a transient analysis.
Figure 5
Below in
figure 6 you will see the Cadence simulation in the Spectre
environment of the four times inverter using the parametric sweep function and
a transient analysis.
Figure 6
Increasing the
capacitive load increases the amount of time it will take for the input signal
to be inverted. As can be seen from the
simulations above the 100fF capacitive load (denoted by the blue line, 1e-13)
is fully inverted by the time the input reaches its peak voltage. On the opposite end of the spectrum the 100pF
capacitive load (denoted by the light blue line, 1e-10) roughly reached 4 volts
after 10ns instead of the intended output of 0 volts.
·
Use UltraSim (Cadence's fast SPICE simulator for larger circuits
at the cost of accuracy) and repeat the above simulations
Below in figure 7 is the simulation of the
single line inverter was repeated using UltraSim and the parametric sweep to
vary the capacitive load.
Figure 7
Below
in figure 8 is the simulation of the 4 times inverter using UltraSim and the
parametric sweep analysis.
Figure 8
Comparing
the UltraSim simulations and the Spectre simulations
you can see they are very similar. For analyzing
a simple circuit, the UltraSim environment is almost as accurate as the Spectre environment.
Conclusion
In conclusion Lab 5 served to provide knowledge in the
construction and simulation of an inverter using NMOS and PMOS design layouts.
My Lab 5 files can be found here to authenticate unique individual
experiments and designs.
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