Lab 4 - EE 421L: Digital Integrated Circuit
Design Laboratory
IV characteristics and layout of NMOS and PMOS
devices in ON's C5 process
Pre-Lab Scope
·
Back-up all of your work
from the lab and the course.
·
Read through Lab 4
before starting it.
·
Go through Tutorial
2.
Lab Work
·
Generate 4 schematics
and simulations:
o A schematic for simulating ID v. VDS of an NMOS
device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5
V in 1 mV steps. Use a 6u/600n width-to-length ratio.
o A schematic for simulating ID v. VGS of an NMOS
device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use
a 6u/600n width-to-length ratio.
o A schematic for simulating ID v. VSD (note VSD
not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps
while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length
ratio.
o A schematic for simulating ID v. VSG of a PMOS
device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again,
use a 12u/600n width-to-length ratio.
·
Lay out a 6u/0.6u NMOS
device and connect all 4 MOSFET terminals to probe pads (which can be
considerably smaller than bond pads [see MOSIS design rules] and directly
adjacent to the MOSFET (so the layout is relative small).
o Show your layout passes DRCs.
o Make a corresponding schematic so you can LVS
your layout.
·
Lay out a 12u/0.6u PMOS
device and connect all 4 MOSFET terminals to probe pads.
o Show your layout passes DRCs.
o Make a corresponding schematic so you can LVS
your layout.
Post-Lab Scope
·
Document the laboratory
exercise and work.
Below are the pre-lab deliverables.
Back-Up Work
Below in Figure 1 you can see I am backing up my work on Google
Drive, as well as on my local computer which is not pictured.
Figure 1
Tutorial
2
Tutorial 2 served as a base reference for proceeding with Lab 4's
experiments.
The design directions of the NMOS were first in the tutorial,
figure 2 below will show the schematic, symbol, layout, and the extracted view
of the NMOS.
Figure 2
The NMOS extracted view was used to run the LVS and the result can
be seen in figure 3 below.
Figure3
ADE simulation was then used to plot ID with a varying VSG. VSG varied from 0-5 V. The graph can be seen below in Figure4
Figure 4
The same process was
followed to design the PMOS. Figure 5
below will show the schematic, layout,symbol and
extracted view of the PMOS.
Figure 5
The PMOS extracted view was used to run the LVS. Below in figure 6 you will see the LVS
passed.
Figure 6
Plotting the ID curve for the PMOS results in figure 7 below.
Figure 7
Post-Lab:
Below are the post lab deliveries.
Schematics and Simulations
A schematic for simulating ID v. VDS of an NMOS
device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5
V in 1 mV steps. Use a 6u/600n width-to-length ratio.
Below in Figure 8 you will see the simulation
schematic used to accomplish the above task.
Figure 8
Below in Figure 9 you will see the resulting
graph of the simulation.
Figure 9
A schematic for simulating ID v. VGS of an NMOS
device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use
a 6u/600n width-to-length ratio.
Below in figure 10 you
will see the schematic view used to accomplish the above task.
Figure 10
Below in figure 11 you
will see the resulting graph of the simulation.
Figure 11
A schematic for
simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS)
varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV
steps. Use a 12u/600n width-to-length ratio.
Below in Figure 12 you will see the simulation
schematic used to accomplish the above task.
Figure 12
Below in figure 13 you will see the resulting
graph of the simulation.
Figure 13
A schematic for simulating ID v. VSG of a PMOS
device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again,
use a 12u/600n width-to-length ratio.
Below in Figure 14 you will see the simulation
schematic used to accomplish the above task.
Figure 14
Below in figure 15 you will see the resulting
graph of the simulation.
Figure 15
Lay out a 6u/0.6u NMOS device and connect all 4
MOSFET terminals to probe pads (which can be considerably smaller than bond
pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the
layout is relative small).
o
Show your layout passes
DRCs.
o
Make a corresponding
schematic so you can LVS your layout.
Below in figure 16 you will see the schematic,
layout and extracted view of the NMOS described above. **the metal 3 in the
layout and extracted views run to a pad**.
Figure 16
Below in figure 17 you
will see the DRC and LVS of the NMOS seen above.
Figure 17
Lay out a 12u/0.6u PMOS device and connect all 4
MOSFET terminals to probe pads.
o Show your layout passes DRCs.
o Make a corresponding schematic so you can LVS
your layout.
Below in figure 18 you
will see the schematic, layout and extracted view of the NMOS described above.
**the metal 3 in the layout and extracted views run to a pad**.
Figure 18
Below in figure 19 you
will see the DRC and LVS of the NMOS seen above.
Figure 19
Conclusion
In conclusion Lab 4 served to provide knowledge in the
construction and simulation of NMOS and PMOS design layouts.
My Lab 4 files can be found here
to authenticate unique individual experiments and designs.
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