Lab 3 - EE 421L: Digital Integrated Circuit Design Laboratory



James Mellott

mellott@unlv.nevada.edu
09/14/2016  


Lab description:

Layout of a 10-bit digital-to-analog converter (DAC) 

 

Pre-Lab Scope

 

·        Back-up all of your previous work from the lab and the course.

·        Finish Tutorial 1

 

Lab Work

·         This lab will focus on the layout of the 10-bit DAC you designed and simulated in Lab 2

Post-Lab Scope

·         Use the n-well to layout a 10k resistor as discussed in Tutorial 1 

o    Discuss, in your lab report, how to select the width and length of the resistor by referencing the process information from MOSIS

·         Use this n-well resistor in the layout of your DAC

o    Discuss, in your lab report, how the width and length of the resistor are measured 

·         Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked)

·         All input and output Pins should be on metal 1

·         DRC and LVS, with the extracted layout, your design (show the results in your lab report)

·         Zip up your final design directory and place it in the lab3 directory, with a link on your lab report, so the grader can examine both the layout and schematic (and simulations)

Pre-Lab:

Below are the pre-lab deliverables.

 

 

In figure 1 you will see that I am backing up my files on google drive, not pictured is the local files I have as well.

 

Figure 1

 

Post-Lab:

Below are the post-lab deliverables.

 

In figure 2 below you will see the n-well layout view and figure 3 will show the extracted view displaying the resistance of the n-well.

 

Figure 2

 

Figure 3

 

Below in figure 4 you can see the layout view for the resistive ladder I am going to use for my DAC.  Figure 5 will show the extracted view for the layout.  The extracted view has a resistance of 10.18k ohms on each n-well resistor, as expected from the single extracted view.

 

 

     Figure 4         Figure 5

 

Below in figure 6 you will see the schematic layout for the resistive ladder network.  This is the schematic that will be used in the LVS.

 

Figure 6

 

Below in figure 7 and 8 you will see the successful DRC and LVS respectively.

 

Figure 7

 

Figure 8

 

 

Discuss, in your lab report, how to select the width and length of the resistor by referencing the process information from MOSIS.

 

Figure 9 below was taken from the C5 process constraints.

 

Figure 9

 

Which leads to the minimun length/width being:

** Lambda: 300nm **

Minimum n-well width: 12*Lambda = 3.6 microns

Sheet resistance of an n-well: 800 Ohms/square

Also recall resistance equation: R = (p*L/A) = (p*L/(t*W)) = (R/sq)*(L/W)

To select the dimensions for a 10k n-well resistor, let the width W = 4.5um

Therefore:

R = (R/sq)*(L/W) = (800 Ohms/sq)*(L/4.5um) 

Solving for L yields --------> L = 56.25um

The n-well resistor must have a length of L = 56.25um

Because the grid spacing is set to 0.15 microns, the L and W dimensions will need to be rounded up or down to the nearest number that can be divided by .15 and have no remainder.

 

 

Simulations:

 

Below will be simulations demontrating the operation of my DAC.

 

Figure 10 below is the DAC schematic with a 10pF capacitive load on the output.  Figure 11 is the result of the simulation which demonstrates that a 10pF load introduces a time delay of 70ns as calculated in my Lab 2.

 

Figure 10

 

Figure 11

 

Figure 12 below is the DAC schematic altered to have a 10k resistive load.  This 10k resistive load acts as another voltage divider.  As you can see below in figure 13 the output is halved again from 2.5v to 1.25v on the output.

 

Figure 12

  

Figure 13

 

Conclusion:

 

In conclusion the DAC designed simulates as intended, and the layout extracted view demonstrates a resistance withing desired specifications.

Click here to download the zip file of my Lab 3 cadence files.

 

 

 

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