Lab 2 - EE 421L: Digital Integrated Circuit
Design Laboratory
Design of a 10-bit digital-to-analog converter (DAC)
·
Back-up all of your work
from the lab and the course.
·
Read through this entire
lab write-up before doing the pre-lab
o Simulate the ideal 10-bit Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC).
·
Prior to coming to lab
make sure you understand how the input voltage, Vin, is related to B[9:0] and Vout.
·
In your lab report:
1. Provide a narrative of the prelab steps.
2. Provide, and discuss, simulation results
different from the prelab illustrate your understanding of the ADC and DAC.
3. Explain how you determine the least significant
bit (LSB, the minimum voltage change on the ADC's input to see a change in the
digital code B[9:0]) of the converter. Use simulations
to support your understanding.
·
Backup your webpages and
design directory.
Lab Work
·
Use n-well resistors to
implement a 10-bit DAC based upon the topology seen in Fig. 30.14,
below, in the CMOS book.
·
Your lab report should
document the following:
o The design of a 10-bit DAC using an n-well R of
10k
·
How to determine the
output resistance of the DAC (answer: R) by combining resistors in parallel and
series
·
Delay, driving a load
o Ground all DAC inputs except B9. Connect B9 to a
pulse source (0 to VDD) and show, and predict using 0.7RC, the delay the DAC
has driving a 10 pF load
o Verify the simulation results match your hand
calculations
·
How to create a symbol
view for your design with the exact same footprint as the Ideal_10-bit_DAC
symbol view.
·
Simulations to verify
your design functions correctly.
o Copy the schematic cell view sim_Ideal_ADC_DAC
to a cell sim2_Ideal_ADC_DAC and replace the ideal DAC with the one you just
designed.
o Use the sim2_Ideal_ADC_DAC to illustrate that
your design works as expected.
o Show what happens if the DAC you designed drives
a load (both R, C, and R/C)
o Explain what happens if the DAC drives a 10k
load?
·
In a real circuit the
switches seen above (the outputs of the ADC) are implemented with transistors
(MOSFETs).
o Discuss what happens if the resistance of the
switches isn't small compared to R.
Pre-Lab:
Below are the pre-lab deliverables.
ADC/DAC
Voltage Relationships:
The
voltage Vin, Vout, and B[9:0]
are related by the following:
Vin
is the analog input to the ADC, the ADC takes the continuous signal and
compares the incoming voltage against a reference voltage divider network. Comparators then switch on or off depending
on the input voltage. What you get as an
output is a digital representation of Vin designated as signal B. B[9:0] is a discrete
time signal. In this lab B is 10-bit representation of Vin and can encode with
a resolution of 1024 bits. That is
derived from the equation (2^n = 2^(10) = 1024
bits); where n is a 10 bit word. B
is then fed into a DAC which consists of a resistive ladder network and
transistor switch setup. The switching
is done based on the values of B, the ladder can take the digital signal and
represent it as a time discrete signal, Vout. Vout is the analog
output of the DAC and represents the digital signal from the ADC in analog
form. In figure 28.1 below is a diagram
taken from the CMOSedu 3rd Edition course
book that illustrates the entire process.
In figure 1
you will see that I am backing up my files on google drive, not pictured is the
local files I have as well.
Figure 1
In figure 2
below you will see that I unzipped the file per the pre lab instructions.
Figure 2
In figure 3
below I am showing that I am opening up the correct file to simulate, and
figure 4 is the result of the simulation before modifications are made.
Figure 3
Figure 4
Below in
figure 5 I am modifying the amplitude of the input voltage to see how it
effects the output. As you can see below
in figure 6 the output voltage appears to be clipping, that is because the
input voltage exceeds the encoding range of the ADC.
Figure 5
Figure 6
Table of Parameters
|
Parameter |
Vin |
Vin’ |
|
Offset Voltage |
2.5 |
2.0 |
|
Amplitude |
2.5 |
4 |
|
Frequency |
2Mhz |
1Mh |
LSB
Determination
The following is a brief discussion on how to determine the Least Significant
Bit (LSB) for the ADC.
Recall: Since
the ADC must quantize and infinite-valued analog signal, the following
expression must be satisfied:
Q =
Number of Quantization Levels = 2^n = 2^(10) = 1024
values
which
corresponds to the 10-bit digital code.
Recall: The
calculation for determining the voltage corresponding to 1 LSB:
1
LSB = VRef/(2^n); where 2^n = Q
1
LSB = (5V)/(1024 Bits) = 4.882813 mV/Bits
Below in
figure 7 I modified the input parameters again.
The results are shown in figure 8.
As you can see the modification was to demonstrate the LSB calculation. Where a 5mv change represents 1 bit. Figure 7 is the modification of the input voltage. Figure 8 is the output voltage, notice the
output is either on or off.
Figure 7
Figure 8
Table of Parameters
|
Parameter |
Vin |
Vin’ |
|
Offset Voltage |
2.5 |
2.5m |
|
Amplitude |
2.5 |
2.5m |
|
Frequency |
2Mhz |
2Mhz |
Post-Lab:
Below are the post-lab deliverables.
Design 10-bit
DAC:
Initially I
started with designing the schematic view of the resistive ladder that I will
make a symbol out of to design the ladder network needed for the DAC.
Figure 9 is the
schematic view, and figure 10 is the symbol view.
Figure 9
Figure 10
From the
symbol I created a new schematic as seen in figure 11 which represents the
resistive ladder network needed for the DAC.
Figure 12 is the symbol created from figure 11.
Figure 11
Figure 12
I then copied the
Ideal ADC/DAC file so I could replace the Ideal DAC with the one I had created
as seen above in figure 12. Figure 13
below is the ideal schematic and figure 14 is the schematic with the replaced
DAC for simulation purposes.
Figure 13
Figure 14
Finally, the
simulation results are displayed below in figure 15. The simulation results nearly match the ideal
simulation results seen from figure 4 in the pre-lab section of this
report. The initial value of the output
voltage in my simulation results start at a lower value then intended this is
why the voltage jumps to roughly 2.6V to match the input voltage.
Figure 15
I also created the n-well layout view of the resistors as seen below. In figure 16 shows the result of first doing
a layout of a single n-well and then creating the layout view of the schematic
seen above in figure 9 of this lab report.
Figure 17 shows the extracted results displaying the resistance of each
n-well resistor. The results show a
value of 10.18K Ohms.
Figure 16
Figure 17
Below in figures 18 and 19 show the successful DRC and LVS results
respectivly.
Figure 18
Figure 19
DAC Output Resistance:
The following is a method for determining the ouput
resistance of the DAC.
For the given topology in Figure 30.14, the DAC output resistance,
can be calculated by it’s Thevenin
Equivalence.
The resultant resistive ladder diagram impedance as seen from Vout is then expressed as:
Rout = ((((((((..................||2R)+R)||2R)+R)||2R)+R)||2R)+R)||2R
Which yields, for any value R in the same topology: Rout =
R
Delayed Load Driving:
The following is a comparison between simulation results and hand
calculations:
For the given topology in Figure 30.14, the DAC time delay, from
B9 to bout with a 10pF capacitive loading can be calculated.
The time delay calculation will be performed in a similar manner
to the DAC output resistance method presented above.
All pins are to be grounded except for b9, which will serve as the
input to the time delay signal to be measured.
The schematic view for the simulation can be seen below in figure 20.
Figure 20
By the Thevenin Equivalence principle
and series/parallel reduction, it is evident that: Vout
= Vin*(2R/(2R+2R)) = Vin*(1/2)
Since Vout must be (Vin/2) for this
configuration of the topology, the output signal 50% points must correspond to
Vout50% = (Vin/2)*(50%) = (Vin/4)
Consequently, this is where the time delay output signal will be
measured up to.
Recall the distributed quantity RC transmission line model and
Time Delay Calculation for Figure 2.22 seen below.
Td = 0.7*R*C*(L*(L+1)/2)
Where
R = 10k Ohms, C = 10pF, L=1
Thus the expected time delay is:
Td = 0.7*(10k)*(10pF) = 70nS
Seen below in figure 21 is the
simulation results verifying hand calculations.
Figure 21
Simulations Demonstrating Correct Functionality:
Below in figure 22 the simulation schematic was altered by having the DAC
drive a capacitive load. As you can see
from the simulation results shown below in figure 23 a capacitive load creates
time delay. As the capacitance of the load increases the time delay increases.
Figure 22
Figure 23
Below in figure 24 the simulation schematic as altered by having the DAC
drive a resistive load. As you can see from
the simulation results below in figure 25 a resistive load alteres the output
amplitude. Where a large resistive load
will not have much effect on the output but as the resistance deacreases the
output voltage decreases. Simulation was
done with a 1k resistor and there was almost no output.
Figure 24
Figure 25
Below in figure 26 the simulation schematic as altered by having the DAC
drive a resistive and capacitive load.
As you can see from the simulation results below in figure 27 a
combination load alteres the output amplitude and introduces a time delay.
Figure 26
Figure 27
Explain what happens if the DAC
drives a 10k load?
If
the DAC drives a 10k load this will act as a voltage divider and the output
will be 50% of what is expected.
In a real circuit the switches
seen above (the outputs of the ADC) are implemented with transistors (MOSFETs).
- Discuss what happens if the resistance
of the switches isn't small compared to R.
This
will cause loading effects that will have an impact on the output. In this scenario the effect will result in a
smaller output voltage.
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