Lab 7 - EE 421L
Carlos Lemus
11/16/2016
Pre-lab work:
- Back-up all of your work from the lab and the course.
- Go through Tutorial 5 seen here.
- Read through the lab in its entirety before starting to work on it.
Lab Description:
- This lab will be about using buses and arrays in designing inverters, MUX/DEMUX, full adders, and other logic gates.
Lab Report should include:
- Schematic of the 8 bit logic gates.
- Simulation of the operation of the 8 bit logic gates.
- Logic gate operation when driving a load.
- Schematic and simulation of MUX/DEMUX.
- Schematic, layout, and simulation of a full adder.
- Also symbols for all schematics made.
Pre Lab work
1. First we went through tutorial 5 and made a ring oscilator of 31 inverters connected in series.
2. We can now plot the ring oscilator
3. The oscilator is easier to visualise when creating a bus schematic
for it. Along with it we can create a layout,drc, lvs, and symbol for it
4. No we can simulate the symbol from the schematic left, and extracted right
5. We further explore using buses and arrays by creating an array of 4
inverters. We perform simialr actions to what we did with the ring
oscilator, making sure that the pins match up to the instance name (
which is 3 to 0)
6. Now we can simulalte the different inverters by selecting seperately
their pins and trying them on a a capactive loads. The capacitors
affect the rise and fall time because of the capacitor. The bigger the
load the higher the delay.
Lab Part 1
1. For this part we
create 8 bit logic gates (NOT,NAND,AND,NOR,OR), the same process
follows as in doing the inverter. We follow a very similar effect to
the oscilator
2. We can test all the gates at once by putting a A and B
inpulse through the gates and testing them the same we wid with the
inverters
3. The plot below shows correct logic for the gates through eac capacitance load
No Load
|
100 pf Lod
|
 |
 |
500 fF Load
|
1 pF Load
|
 |
 |
Part 2
1. Now we create a MUX/DEMUX. The schematic and symbol are shwon below
2. We can simulate the full adder similar to the gates by trying varying voltage pulses for each input
3. This is a 2 to 1 MUX where two inputs control the signal and gives
an out put. 0 selects A and 1 selects B. We can see that Si is only an
inverse of S so we can add an inverter to our schematic and create a
new symbol.
4.Again we can simulate and should get the same waveform
5.We can also test the DEMUX
6. Now we build an 8 bit MUX and simulate it using busses. We test two of the inputs.
Part 3
1. This
final part was to create a full adder circuit. The figures below are
interconnected, but seperated for simplicity. The left shows carry out
and right shows the sum.
2. We create a full adder symbol
3. Next we can simulate schematic using the symbol. and get something simlar to the table below
A
|
B
|
Cin
|
Sum
|
Carry
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
1
|
1
|
1
|
4. We layout the schematic as shown below, DRC it and LVS
5. Next we make an 8 bit adder instantiating the 1 bit adder and using
busses and wires. The Cn_1<7> represents the last carry out bit.
and Cn represents the first carry in bit. The rest of the carry out
bits are connected to the input of next Carry in.
6. We create a symbol for the 8 bit adder
7. Next we create our layout of the 8 bit adder. Notice the label on the pins
8. We DRC and LVS
9. Next we can simulate the 8 bit Full adder to see the carry out bits
delay through the full adder to get an output carry_out and sum
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