Lab 6 - EE 421L
Carlos Lemus
lemus@unlv.nevada.edu
October 26, 2016
Pre-lab work:
- Back-up all of your work from the lab and the course.
- Go through Tutorial 4 seen here.
- Read through the lab in its entirety before starting to work on it.
Lab Description:
- This lab will be about the design, layout, and simulations of a CMOS logic gates.
Lab Report should include:
- Schematic, and layout of the CMOS inverter.
- Schematic, and layout of the CMOS NAND gate.
- Schematic, and the layout of the CMOS XOR gate.
- Schematic, and the layout of the CMOS Full Adder.
- All layouts with LVS match and DRC no errors.
- Simulation of all the possible logic inputs of the gates.
Expertiment 1
- We first copy over our inverter from lab5
- Bellow is the schematic of the inverter and symbol used
- Includes : Layout, extracted, DRC, and the LVS
Experiment 2
- The inverter is important to learn because it is used heavily in the following schematics
- Below is the schematic, symbol, simulations, layout ,extracted layour, DRC, and the LVS for the NAND gate
- .
With one input at VDD we can see that the graph alternates when "in" is
high a AND gate is 1 and the NAND makes it 0. The VDD is set to 5V by
the global net.
Experiment 3
- Similarly to the NAND gate we will make an XOR that has similar components to the inverter
- The no connection of Ai and Bi connects to the Ai and Bi labels
of the PMOS and NMOS respectively in on the right side of the XOR
- Below shows the symbol, layout, extracted layout, DRC and LVS
To simulate the gates we will put all the gates together and simulate to test out each one. The gates
A
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B
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Not A
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NAND
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XOR
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0
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0
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1
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1
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0
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0
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1
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0
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1
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1
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1
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0
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0
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1
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1
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1
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1
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0
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0
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0
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The plot below shows the gates functionality working properly,
comparable to the table. The XOR shows a glitch that could be due to
timing issues.
Experiment 4
- Finally, we will make a full adder using the gates we have for the NAND and XOR gates
- The symbol for the FA was created with 3 inputs and 2 outputs
3. We will also use the NAND and XOR layouts to
reconnect multile together to create the schematic shown below
5. We will then LVS and DRC to the schematic.
Now that the layout is complete we can test out the FA.
First we test the schematic
a
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b
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cin
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s
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cout
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0
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0
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0
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0
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0
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0
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0
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1
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1
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0
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0
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1
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0
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1
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0
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0
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1
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1
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0
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1
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1
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0
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0
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1
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0
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1
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0
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1
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0
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1
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1
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1
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0
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0
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1
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1
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1
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1
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1
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1
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And now the extraced simulation
BACK UP
Lab 6 zipfile
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