Lab 4 - EE 421L 

Carlos Lemus

lemus@unlv.nevada.edu

October 5, 2016 

Pre-lab work:

• Back-up all of your work from the lab and the course.
• Go through Tutorial 3 seen here.

• This lab will be about the design, layout, and simulations of a CMOS inverter.

• Schematic of the CMOS inverter.
• Layout of the CMOS inverter.
• LVS match and DRC no errors of the layout.
• Spectre simulations of the inverter along with capacitive loads.
• UltraSim simulations of the inverter along with capacitive loads.

• The prelab was to go through tutorial 3 and create a CMOS inverter using a PMOS and NMOS
  
• The PMOS had a size of 12u/6u
• The NMOS had a size of 6u/6u
• Below shows of the single multiplier schematic and extracted inverter
  

• We reate a new symbol for the schematic then DRC and LVS

• For the lab we just multiply the MOSFET sizes to 4 to create a 48u/24u inverter
• Explanation of the layour
• Notice the Source of the PMOS connected to power (vdd!)
  
• The ground (gnd!) is connected to the ptap cell below the NMOS
• The layout has 4 pins: A, Ai, vdd!, and gnd! (lowercase letters are used for power and ground

• Then we create a symbol for the 48u/24u inverter and  LVS and DRC

Part 2

• Now that we have the layouts matching with our symbols we can start the simulations. Using a spectre and UltraSim which can only be done in transient analysis.
• Below is the schematic and  simulations for th12u/6u inverter changing the capacitor respectively
  

• Notice there isn't much difference between the Spectre and UltraSim in these images, but UltraSim gives more accurate waveform output.
  

	Spectre	UltraSim
100fF
1pF
10pF
100pF

• Now we perform the same experiment usiung the second CMOS inverter, which has the widths of both the NMOS and PMOS multiplied by 4.
  

	Spectre	UltraSim
100fF
1pF
10pF
100pF

Discussion

• We notice that the outpus is inverted . (Also note, thoug not shown in the graphs the inverter will only draw current during switching of voltages.
• As the capactive load increases the bigger the RC circuit delay. This means it takes longer for the capacitor to charge. If we increased the time of our pulse width we would see the bigger capacitor slope still invert instead of cutting off.
• We can see from the first imverter it takes less time for the inverter to change

The lab backup was saved to Google Drive, and the zip is attacked below

Lab 5 zipfile
 

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