Lab 3 - EE 421L 

Carlos Lemus

lemus@unlv.nevada.edu

September 21, 2016

  

Pre-lab work:

Lab Description:
Lab Report should include:



LAB

Part 1

    1. First thing I did was copy all my files from Lab 2 to my Lab 3 library.
     2. Then I layed out the 10k n-well resistor. Selecting the length and width for the resistance requires Resistance formula and knowing the MOSIS 800 ohms/square sheet resistance and that the minimum width of n-well is 12 lambda (3.5 microns since lambda is 300nm). Knowing this, we can use the following equation to calculate a ratio that will result in 10k.
     3. We could pick 4.5 um for the width and 56.25 um for the length but the grid uses an x and y snapping of .15 so we need to choose 56.1 to get a whole number



formula

10k_n_well

The extracted view above shows the actual resistance created by n-well which can be shown to be approximately 10k (10.21k).



Part 2

 
For this next part we are going to start laying out the DAC with the 10k n_well resistor that we created. We first need to create the bottom resistor divider of the DAC.

Notice below that the second resistor shows the pin named B0 and the the bottom 4 represend the 2R-2R resistors that hang at the bottom of the DAC.

dac_layout

Then notice there is a metal1 layer that connects to the 2R to the B1 2R, shown more below. The whole layout was easily created once the first two pins(B0, and B1) and 2R-R circuits was created then the copy function was used to create 6 more columns in the upward direction. This instantly created the entire DAC system.

dac_layoutcopy

The DAC system was DRC and LVS to generate the netlist with the Lab2 2R-R DAC system schematic that was created. The layout is now connected to the pins and resistors in the schematic shown below and a the symbol was updated:

lvsdrc

Then we can connect the  DAC symbol to the ADC . Note the symbol is now using the extracted version of the schematic, not the resistor schematic.

schem

To use the extracted schematic in our simulations we must change the environment options. Notice the "extracted" before the schematic in the view list.


extracted_sim


Check the netlist to make sure we are using the extracted version instead of the schematic.

netlist


Experiment #3: The Sims

Simulations are as followed .
    1. Replacing the ideal DAC with the extracted version (no loads) it is virtualy the same. I've changed the Vout to be blue and Vin to be Red in the extracted layouts.
    2. Creating a pulse on pin B9 with other grounded
    3. This is the ADC and DAC schematic with a 10k load
    4. This is the ADC and DAC schematic with a 10pf load
    5. This is the ADC and DAC schematic with both of the 10k and 10pf loads

Take note that each one is not described in detail because they are the same as LAB 2 and is as expected.


Simulations from the schematic
Simulations from the extracted layout
1
Schematic noload
no-load-extracted
2
delat
delay2
3
10k
resload
4
capcitor
cap_load_plot
5
both
both



The files have been backed up

save


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