lab1

Lab 7 - EE 421L

Kristal Lemieux

Nov. 16, 2016

Pre-lab work:

· Backed-up all of your work from the lab and the course.

· Tutorial 5 was to create a 30 ring oscillator.

· In order to create a 30 ring oscillator without repeating the symbol, we used buses(wide wire”). Then we layout the 30 ring oscillator ensuring it DRCs and LVSs correctly.

Layout View of 30 Ring Oscillator

Extracted View of 30 Ring Oscillator

Zoomed In of Oscillator

DRC passed with no errors.

Netlist Match

Simulation from Schematic Simulation from Extracted

Post Lab:

· Now we create a 4-Bit inverter using a bus and naming the bus making an array.

· A symbol is then created from the cell view of the 4-Bit inverter.

· To test this inverter, we connect the loads to three out of four input pins with a pulse input.

Inverter Circuit 4-Bit Inverter

· The capacitive load affects the rise and fall time by the delay created from the capacitor. The bigger load the more delay there is. When we compare the 100fF to 1pF, the delay in the one 1pF is more apparent. This is because when the capacitive load is higher the inverter the load.

· The next part of this lab is to create a number of 8-Bit logic gates in a process that is similar to creating the inverter. Seen below are NAND, NOR, AND, and OR gates schematics and corresponding symbols.

NAND Circuit 8-Bit NAND

NOR Circuit 8-Bit NOR

AND Circuit 8-Bit AND

OR Circuit 8-Bit OR

· To test the 8-Bit gates we do what we did with the 4-Bit inverter: Add a pulse and capacitive loads.

· We can see how different loads affects different gates in the simulations

No Load 100pF Load

500pF Load 1pF Load

· MUX/DEMUX schematic and symbols are seen below.

· There is a control, 2 input, 1 output. The value depends on the switch changing between two inputs with the control signal.

· The operation of the MUX/DEMUX can be seen in the simulations below. When S is low then Z is the same as B. Then when S is high Z is the value of A.

· Seeing that S and Si are the same as having an inverter between both inputs. We added an inverter from the beginning of this experiment and made a new symbol. This would create a DEMUX.

MUX Schematic MUX symbol

MUX simulation

· Now if we do the same schematic done above we would get the same exact waveform.

· The following is the schematic for a DE-MUX as well as the waveform output to show its operation.

· We see that the input signal is from Z, and the controlling factor here is S. When S is high the input Z outputs from A which output B is random, and when S is low Z outputs in B which A is random.

· Now we make an 8 bit MUX/DEMUX, using the schematic that includes the inverter and creating symbol using bus wires and instance name as an array.

· We use the symbol created and have different inputs at two pins from the 8 bit MUX. The output waveform is shown below and verifies that the MUX works properly.