Lab 6 - EE 421L
·
Back-up all of your work from the lab and
the course.
·
Go through Cadence Tutorial 4.
Lab:
We were
instructed to name our cell views with our initial and semester year. I renamed
all the cell views at the end and screenshotted my library manager to show that
I did this.
Inverter
·
By doing the prelab, we created schematics, symbols, and layouts
for an inverter and NAND.
·
The inverter was created with a 12u/.6u NMOS and PMOS.
·
The layout view DRCd with no errors.
After extracting it I then LVSd the schematic and extracted
views and the netlist matched!
·
Seen below are zero errors for the layout and the netlist for the
inverter.
o (inverter =
INVERTER_KL_f16 in my library manager. I renamed the cell views after I took
all the screen shots..)
NAND
·
Next, I created the NAND gate. This was created using two 12u/.6u
PMOS’s and two 12u/.6u NMOS’s. The schematic is seen below with the
corresponding symbol.
·
The layout was then made for the NAND DRCd
with no errors. The extracted view of the layout is right beside the layout
view.
·
The LVS show that the netlist match from the schematic to the
extracted. This is shown below along with the netlist.
o (nand2 =
NAND_KL_f16 in my library manager )
·
Simulating the NAND we see it is working properly. VDD put in an
input of one while the in is pulsing between one and
zero.
·
We see that input 1 and 0 outputs 1 and input 1 and 1 outputs 0
from the simulation. Thus, the NAND is working correctly.
o Logic table
for NAND:
XOR
·
The XOR was created with multiple PMOS’s and NMOS’s seen in the
schematic below.
·
Below schematic the left side there is a two
inverter schematic to invert A and invert B. The output of the inverters
do not have a connection so I put a pin there to let
the program know that it was not floating.
·
The schematic, layout, and extracted views showed DRC with no
errors. When LVS was ran the netlist matched!
o (XOR2 =
XOR_KL_f16 in my library manager)
·
These are the values I got when working out the logic in my head
for the inverter, NAND, and XOR. The simulations match the logic of the gates
so we can now create the Full-Adder!
|
A |
B |
Ai |
AnandB |
AxorB |
|
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
1 |
|
1 |
1 |
0 |
0 |
0 |
Full-Adder
·
I now use the gates to create the Full-Adder. From the schematic I create a symbol with three inputs and two
outputs.
·
Shown below is the layout I created for the schematic. To do this
I instantiated the layouts for the NAND and the XOR and connected them as
needed.
·
It DRCd with no errors. When extracted
and compared to the schematic using LVS the netlists matched!
o (FA2 =
FA_KL_f16 in my library manager)
·
The first simulation is from the schematic of the Full-Adder.
·
Again working out
the logic, for the inputs the resulting outputs will be as seen below from the
table.
|
a |
b |
cin |
cout |
s |
|
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
1 |
|
0 |
1 |
1 |
1 |
0 |
|
1 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
0 |
1 |
|
0 |
1 |
0 |
0 |
0 |
|
1 |
1 |
0 |
1 |
0 |
·
As you can see from the simulation from the schematic, the logic
matches the predicted values for the Full-Adder!
·
The simulation below is the extracted view from the layout. This
matches the schematic simulation perfectly!
·
There are some glitches in the simulations. This is due to the
timing of the gates. Each gate has its own delay, therefore, causing a slight
delay for the output.
In this lab
we designed a 2-input NAND gate, XOR gate, and Full-Adder. We did this with
components that we have been using to build up to this lab since the
beginning of the semester. The use of NMOS’s and PMOS’s allowed us to create
the correct logic gates. The devices were successfully DRCd,
LVSd, and simulated with the schematic and extracted
views.
Files can be found in lab
6