Lab 5 - EE 421L
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Back-up all of your work from the lab and the course.
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Go through Tutorial 3
Lab
Description:
·
Draft schematics, layouts, and symbols for two inverters having
sizes of:
o 12u/6u (=
width of the PMOS / width of the NMOS with both devices having minimum lengths
of 0.6u)
o 48u/24u where
the devices use a multiplier, M = 4 (set along with the width and length of the
MOSFET, image), as seen below
Inverter 12u/6u
The first
design was a 12u width/6u length inverter. I connected a NMOS of 12u/6u and
PMOS of 6u/.6u to create an inverte(Figure 1) then made a symbol from the schematic as seen in
figure 2. The symbol is an easier way to reference the NMOS and PMOS.
Especially when we simulate it.
Figure1 Figure
2
I then created
the layout view for the inverter making sure the vdd!, gnd!,
A and Ai pins were in the correct area. It DRC’d with
zero errors seen in Figure 3. I then extracted the layout and ran a LVS
verifications. The LVS job was completed and the net-lists from the extracted
view compared to the schematic matched (Figure 5). The netlist can be seen in Figure 6.
Figure 4 Figure
5
Figure 6
48u/24u Inverter
The same
approach was used to create a 48u/25u inverter with the Multiplier being
four(M=4). The schematic of the inverter was drafted then a symbol was created
from the schematic as seen in Figure 7 and Figure 8.
Figure 7 Figure
8
I then created
the 48u/24u layout for the inverter. DRC’d it with
zero errors and extracted it. Once I extracted it, I ran LVS to make sure the
netlist matched. When LVS was completed the schematic of the inverter in Figure
7 matched the extracted in Figure 10. The listed netlists are seen in the
netlist summary(Figure 12).
Figure 10 Figure
11
Figure 12
Simulations
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Using SPICE simulate the operation of both of your inverters showing
each driving a 100 fF, 1 pF, 10 pF, and 100 pF
capacitive load
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Comment, in your report, on the results
·
Use UltraSim (Cadence's fast SPICE
simulator for larger circuits at the cost of accuracy) and repeat the above
simulations
·
Use Setup -> Simulator/Directory/Host and select UltraSim as seen below
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You'll also have to point to the MOSFET models again as seen below
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Note that UltraSim only performs
transient simulations (not AC, Noise, DC, operating point, etc.)
·
Not knowing this last item will lead to wasted time if trying to
use UltraSim exclusively for simulations
For these
simulations I am simulating with Spectre and UltraSim. You switch to UltraSim
by launching ADEàSetupàSimulator/Directory
Host as seen below. Also, I have to make sure the proper modal libraries were
chosen for both the NMOS and PMOS. Also seen below, you can go to SetupàModal
Libraries… The schematic will not simulate correctly if you do not add those
libraries.
Figure 12.5
As in the
instructions, the value of the capacitor was changed from 100fF, 1pF, 10pF, and
100pF.
In Figure 13, Cload was the varied capacitor. In the pairs, the first one
is the UltraSim and the second is the Spectre. So for example, Figure 14 would be the UltraSim for the 100fF capacitor and Figure 15 would be the
Spectre from the 100fF capacitor.
Figure 13
The below results
demonstrate that the larger the capacitive load the longer time it takes for
the capacitor to charge and discharge. The time constant = R*C so the larger
the capacitor the larger the time constant as well. Let’s take a look at the
100fF capacitive load. The output is completely inverted of the input. As the
load increases, the output waves start to not be able to invert and it
eventually seems as if it does not invert at all like in Figure 20 and 21.
100fF:
Figure 14 Figure
15
1pF:
Figure 16 Figure
17
10pF:
Figure 18 Figure
19
100pF:
Figure 20 Figure
21
In Figure
21.5, I am now simulating a 48u/24u inverter. As you can see, changing the
capacitive load yields the same results at the 12u/6u inverter previously. With
this inverter, it doesn’t lose its ability to invert as quickly as the previous
one but it still does have the same characteristics.
Figure 21.5
Once again, the
first image of the pair is the UltraSim while the
second is the Spectre. For example, Figure 22 is the UltraSim for the 48u/24u circuit while Figure 23 is the Spectre for the 100fF capacitive load. The higher the
capacitor, the less proficient the inverter to output the opposite of the input
signal.
100fF:
Figure 22 Figure
23
1pF:
Figure 24 Figure
25
10pF:
Figure 26 Figure
27
100pF:
Figure 28 Figure
29
Conclusion
In conclusion,
I drafted two schematics, layouts, and symbols for inverters with the sizes of
12u/6u and 48u/24u that used a multiplier of 4. I made sure the design
specification was met by DRCing and LVSing the the schematic, layout,
and extracted views with zero errors and matching netlists. The results of the
simulations showed me that a bigger inverter can operate more capacitive load.
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