Lab 3 - EE 421L
Prelab:
·
Back-up all of your previous work from the lab and the course.
·
Finish Tutorial 1
Backed up my files in google drive:
Finishing up Tutorial 1 for a 10k resistor:
The DRC and LVS passed.
Post lab:
·
This
lab will focus on the layout of the 10-bit DAC you designed and simulated in
Lab 2
·
Use
the n-well to layout a 10k resistor as discussed in Tutorial 1
·
Discuss,
in your lab report, how to select the width and length of the resistor by
referencing the process information from MOSIS
·
Use
this n-well resistor in the layout of your DAC
·
Discuss,
in your lab report, how the width and length of the resistor are measured
·
Ensure
that each resistor in the DAC is laid out in parallel having the same
x-position but varying y-positions (the resistors are stacked)
·
All
input and output Pins should be on metal 1
·
DRC
and LVS, with the extracted layout, your design (show the results in your lab
report)
·
Zip up
your final design directory and place it in the lab3 directory, with a link on
your lab report, so the grader can examine both the layout and schematic (and
simulations)
To design the 10k resistor in the C5
Process, the width of 4.5 um and 800 ÿ’s was used for the equation R = 
à 10k = 800 x 
,
L= 56.25um. I rounded down since everything has to be in increments of 0.15.
This would make my L = 56.1um. Contacts were added to both ends of the resistor
that connected to metal1. I put a res_id layer on top of the n-well layer so that when I extract
the view cadence will recognize it as a resistor. I then created pins for the
left and right sides of the resistor named “L” and “R” in the metal1 layer.
Using the n-well resistor from tutorial 1,
I built a resistive layout to design my DAC.
Seen below is my layout view, extracted
view, and a few of the resistors properties to show that they are all at the
same point on the x-axis. All the BX input pins and output pins are on the
metal1 layer.
Schematic of the
Resistive ladder DAC
symbol for resistive ladder
DRC showing zero
errors! LVS
passed!
Values from LVS
I replaced the DAC created with the n-well resistors
in the schematic from last lab where we designed a 10-Bit DAC to show
simulations match. In lab 2, my DAC was named 10-Bit while in this lab it was
simply named DAC. You can replace symbols by deleting the one you want to
replace and adding an instance, going to the library where your symbol is saved
and placing it.
My DAC design connected to ADC and the
simulation results.
In Figure 1(a) and 1(b), my DAC is
connected to the ideal ADC. As you can see compared to the “10-Bit” created
last week in Figure 2(a) and 2(b) the simulations come out the same.
Figure 1 (a) Figure
1 (b)
Figure 2 (a) Figure
2 (b)
I did a few
more exercises to ensure that my DAC with the n-well resistors was simulating
correctly.
Driving a load:
Just like last
week, I connected B9 to a pulse source, add a 10 pF capacitor, and ground all
other inputs and predict a delay driving load.
The expected
time delay should be 70ns.
Figure 3(b)
and 4(b) have the same simulation results.
Figure 3 (a) Figure
3 (b)
Figure 4 (a) Figure
4 (b)
Simulations
to verify:
Resistive
load:
The simulation
shows the output voltage being about half the input for both the n-well
resistor DAC created this week Figure 5 (b) and the DAC created last week
Figure 6(b)
Figure 5 (a) Figure
5 (b)
Figure 6 (a) Figure
6 (b)
Capacitor load:
The output
voltage is still lagging and gets even smaller when you add a capacitor and
resistor load to the circuit as seen in Figure 7(b) from this week compared to
Figure 8(b) from the week prior.
Figure 7 (a) Figure
7 (b)
Figure 8 (a) Figure
8 (b)
Capacitor and Resistive Load:
Simulations in
Figure 9(b) match to the simulations in Figure 10(b) from the 10-Bit DAC created
in lab 2.
Figure 9 (a) Figure
9 (b)
Figure 10 (a) Figure
10 (b)
In conclusion, the DAC work as it expected. To check this I replaced the 10-Bit DAC designed last week with the DAC
created with n-well resistors this week that produced the same simulations.
Zip file from
this lab are located here