Lab 8 - EE 421L
Each test circuit should have its own power but ground should be shared between the circuits.
Ground should be pin 20.
Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable.
The image seen at the bottom of the page shows how the chip's pads correspond to the pins of the 40 pin DIP package we'll receive from MOSIS.
Your chip should include the following test structures:
- One, or more if possible, course projects
- A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
- NAND and NOR gates using 6/0.6 NMOSs and PMOSs
- An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
- Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad)
- Note that only one pad is needed for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
- Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor)
- A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)
- Whatever else you would like to fabricate to use the remaining pins on the chip
- Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Copy the final, DRC and LVS clean cell you want to fabricate, and then add the graphic since the graphic won't DRC
- Also
note that you can reduce the number of pins needed by sharing some
of them (two resistors, for example, only need 3 pins)
Chip Devices
The
chip contains the following devices
- 6u/0.6u PMOS and NMOS devices
| Chip Schematic |
 |
| Chip Layout with passing LVS and DRC |
 |
Testing Manual
- Pin 20 is global ground
- Logic level: 5 V
- NAND Gate (Pints 2, 3, 4, 5)
- Apply logic signals to inputs A and B, to read the output at pin 5. Output should be A NAND B.
- VDD: 2
- A input: 3
- B input: 4
- A NAND B output: 5
- NOR Gate (Pins 6, 7, 8, 9)
- Apply logic signals to inputs A and B, to read the output at pin 5. Output should be A NOR B
- B input: 6
- A NOR B output: 7
- VDD: 8
- A input: 9
- Resistors (Pins: 11, 12, 13)
- 25k n-well resistor: 11, 12
- 10k poly resistor 11, 12
- Note: the resistors are in a voltage divider configuration, sharing pin 12. For example, if only the poly resistor is required, probe at pins 11, and 12 only.
- PMOS Transistor (Pins: 14, 15, 16, 17)
- PMOS sized at a width of 6um by 600nm
- Body: 14
- Source: 15
- Drain: 16
- Gate: 17
- 31 Stage Ring Oscillator (Pins: 18, 19)
- Once powered, the output will output an oscillating clock signal.
- VDD: 18
- Output: 19
- NMOS Transistor (Pins: 22, 23, 24)
- NMOS sized at a width of 6um by 600nm
- Gate: 22
- Source: 23
- Drain: 24
- Inverter (Pins: 25, 26, 27)
- The input logic is inverted at the output.
- Output: 25
- VDD: 26
- Input: 27
- Sequence Detector (Pins: 36, 37, 38, 39)
- With a clock input at CLK, and a serial input sequence, the sequence detector will output a logic high when the input is '101011'.
- VDD: 36
- Input: 37
- CLK: 38
- Detect: 39
- Unusued Pins: 10, 21, [28, 35], 40