Lab 6 - EE 421L
Digital Integrated Circuit Design
Garnerj5@unlv.nevada.edu
10 October 2016
Return to: J.Garner EE421 Labs
Design, layout, and simulation of a CMOS
NAND gate, XOR gate, and Full Adder
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Cadence
Tutorial 4 seen here.
- Read
through the lab in its entirety before starting to work on it
- Draft
the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate
(Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
- Create
layout and symbol views for these gates showing that the cells DRC
and LVS without errors
- ensure that your symbol views are the commonly used
symbols (not boxes!) for these gates with your initials in the middle of
the symbol
- ensure all layouts in this lab use standard cell
frames that snap together end-to-end for routing vdd! And gnd!
- use a standard cell height taller than you
need for these gates so that it can be used for more complicated
layouts in the future
- ensure gate inputs, outputs, vdd!
and gnd! are all routed on metal1
- Use
cell names that include your initials and the current year/semester, e.g.
NAND_jb_f19 (if it were fall 2019)
- Using
Spectre simulate the logical operation of the
gates for all 4 possible inputs (00, 01, 10, and 11)
- comment on how timing of the input pulses can cause
glitches in the output of a gate
- Your
html lab report should detail each of these efforts
NAND Gate Images
Schematic:
Symbol:
Layout:
DRC:
LVS:
XOR Gate Images:
Schematic:
Symbol:
Layout:
DRC:
LVS:
Simulation Results from Logic Gate Analysis:
Schematic:
Simulation:
Here we see when switching the input to a gate too fast can
cause problems at the outputs of the gates. We see this in A XOR B (BLACK),
momentarily switching B from 0 to 1 causes a little bit of a glitch, though our
output should remain 1.
Full Adder
Schematic:
Symbol:
Layout:
DRC:
LVS:
Simulation Schematic:
Simulation Results:
