Lab 4 - EE 421L Digital Integrated Circuit Design

Authored by James Garner

Garnerj5@unlv.nevada.edu

24-25 September 2016

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IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Pre-lab work

• Back-up all of your work from the lab and the course.  
• Read through this lab before starting it.
• Go through Tutorial 2 seen here. 
• In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V.  

Pre Lab

To back up my files I opened CMOSedu in my file explorer, zipped up my previous Lab that I completed (Labs before that were backed up previously) and then emailed the zip file to myself which is seen in the picture below.

Tutorial 1 went over Layout and simulating the IV curves of PMOS and NMOS devices

Lab 4

• Generate 4 schematics and simulations (see the examples in the Ch6_IC61 library, but note that for the PMOS body should be at vdd! instead of gnd!):
• A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
• A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.
• A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
• A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.  
• Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small). 
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout. 
• Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads. 
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout. 
• Some examples are seen below (click for a larger view). 
• They are, in order: 1) probe pad layout, 2) probe pad schematic, 3) probe pad symbol, 4) schematic of the MOSFET with probe pads, 5) corresponding symbol view, 6) corresponding layout (which is DRCed and LVSed), 6) zoomed in view of the layout, and finally 7) simulation schematic for ID v VSD for varying VSG (which is not used for an LVS since there is no way to lay out a battery).  
• These cells are found in lab4.zip

Part One - Schematics/Simulations:

The first thing that my classmates and I noticed that the examples used in Cadence were not setup to properly simulate what we were looking for so we had to create our own schematics which gave us proper results.

The second thing which took me awhile because I forgot/didn’t pay attention was setting up the correct model. This needs to be done as soon as the ADE window is open so that the user doesn’t waste time getting errors.

Each schematic will have pictures in the following order if those pictures apply: Schematic, ADE Window, Parametric Analysis window, Simulation Picture.

Problem I: IDvsVDS NMOS

Problem II: IDvsVGS NMOS

Problem III: IDvsVSD PMOS

Problem IV: IDvsVSG PMOS

Part Two – Layout of NMOS with Probe Pads.

This process was fairly simple seeing because the class was assigned to go through the tutorial and do several lecture problems having to do with NMOS and creating schematics.

I started with instancing a NMOS from the Analog Parts library. Then I continued to change its size and add pins to the respective nodes. Laying down poly and instancing a m1_poly for the gate, m1 for the source and drain, as well as instancing a ptap and adding the base pin to it was the next step.

From there I simply created Via1 and Via2 instances using m2_m1 and m3_m2. I then used Create à Rectangle to attach paths from the NMOS to the probe pads through the via’s. The probe pads were instanced from Dr. Baker’s lab4.zip.

Part Three – Layout of PMOS with Probe Pads

This process followed the process above with the respective complimentary changes between NMOS/PMOS.

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