Lab 3 - ECE 421L
Garnerj5@unlv.nevada.edu
14-17 September 2016
Return to: J.Garner EE421 Labs
Layout
of a 10-bit digital-to analog converter (DAC)
Pre-lab work
- Back-up all
of your previous work from the lab and the course.
- Finish Tutorial 1 seen here.
Pre
Lab
To back
up my files I opened CMOSedu in my file explorer,
zipped up my previous Lab that I completed (Labs before that were backed up
previously) and then emailed the zip file to myself which is seen in the
picture below.
Tutorial
1 went over the process of creating a layout, adding pins to it, and verifying
DRC/Extracted/LVS functions.
Lab 3
This lab will focus on the layout of the 10-bit DAC you designed
and simulated in Lab 2
- Use the n-well to layout a 10k resistor as discussed in
Tutorial 1
- Discuss, in your lab report,
how to select the width and length of the resistor by referencing the
process information from MOSIS
- Use this n-well resistor in the layout of your DAC
- Discuss, in your lab report,
how the width and length of the resistor are measured
- Ensure that each resistor in the DAC is laid out in
parallel having the same x-position but varying y-positions (the resistors
are stacked)
- All input and output Pins should be on metal 1
- DRC and LVS, with the extracted layout, your design
(show the results in your lab report)
- Zip up your final design directory and place it in
the lab3 directory, with a link on your lab report, so the grader can
examine both the layout and schematic (and simulations)
Ensure that your html lab report includes your name and email
address at the beginning of the report (the top of the webpage).
When finished backup your work (webpages and design directory).
N-Well
Resistor (10k) Layout:
The
process in calculating the width and length of the N-Well Resistor is by
following the equation below, where W is width, L is length, R is resistance
and ρ is 800Ω󠄀/󠄀󠄀.
I
prefer to use a width of 4.5 because it lines up nice with the ntap instance used for pins. Therefor I used a W of 4.5,
ρ was given, and R is what we are looking for. This gave me a length of
56.25.
DAC
Layout:
To create my DAC_Layout
I copied my 10kNwell resistor four times, and stacked them on each other. From
there I used the path (p) option to create metal1 paths to connect the ends of
my resistors in the appropriate orientation. From there I copied my three
resistors on the top with their respective metal1 paths nine different times to
get a total of ten metal1 strips on the left side of my layout. After that I
pinned my B0 through B9, my GND! And my Vout.
The process of measuring the length and
width of the resistor is using the ruler function under the Tools tab, hot key
(K). I set up my ruler from end to end and then did the same for the width of
the ruler.
Below are the DRC and LVS verifications
for my DAC_Layout:
Simulations are provided in the table
below to show the difference between Schematic and Extracted Simulations. The
picture above shows how to simulate an extracted view, though the netlist match
two pictures above ensures that we should get the same results from either
simulation.
|
Schematic Simulation |
Extracted Simulation |
|
10K Resistive Load Simulations |
|
|
|
|
|
Capacitive Load Simulations |
|
|
|
|
|
Shared Load Simulations |
|
|
|
|
The LVS match ensures that the
simulations should all be the same whether simulating from the extracted view
or the schematic view.