Lab 7 - EE 421L 
Tyler Ferreira,
ferret1@unlv.nevada.edu
November 15, 2016
  

Pre-lab work

 
Experiment 1:
 
Creating a concise schematic for a 4-bit inverter:
 

 
Creating a symbol for the concise schematic for use in a simulation schematic:
 

 
Creating a schematic to simulate the operation of the 4-bit inverter:
 

 
Simulation results:
 

 
Notice that as the capcitive load is bigger the output is ramping up and down instead of looking like a square wave.
The larger the load the longer the rise and fall times of the voltage across the load.
 
 
Experiment 2:
 
Creating 8-bit logic gate and simulating them:
 

Simulating the operation of an 8-bit NAND gate

Simulating the operation of an 8-bit NOR gate

Simulating the operation of an 8-bit AND gate

Simulating the operation of an 8-bit OR gate

Simulating the operation of an 8-bit Inverter

 
 
Experiment 3:
 
8-bit 2-to-1 DEMUX/MUX

 

Schematic to simulate the operation of the 2-to-1 DEMUX/MUX using my symbol:

 

 

Simulation results: 

 

 

As you can see from the simulation results the output of the circuit will either be A or B depending on what S is. This is how a multiplexer circuit works, there are 2 inputs which are chosen to be sent to the output by the selector variable S.

A DEMUX circuit works by sending one variable into the circuit and using the selector to send that one variable to a select spot. It is the multiplexer circuit but the input is Z and the outputs are A and B.

 

 

Experiment 4:

 

Draft the schematic for the full adder in Figure 12.20 using 6u/0.6u PMOS and NMOS devices.

  

My schematic for the full adder in figure 12.20:

 

 

Symbol created for the above schematic:

 

 

Simulation of the full adder circuit:

 

 

Simulation Results:

 

 

Layout of the full adder:

 

 

LVS and DRC passed:

 

 

Now that I have finished creating the full adder in Figure 12.20 I will use this to create an 8-bit full adder.

 

I will start by creating a concise schematic of the full adder using my symbol for the 1-bit full adder:

 

 

Now I can create a symbol for this schematic:

 

 

Simulation of the 8-bit full adder using the symbol:

 

 

Simulation results:

 

 

Layout of the 8-bit full adder:

 

 

The layout above is just 8 1-bit full adder circuits connected to each other. The Cn+1 of the 1st adder is connected to the Cn of the next adder.

 

LVS and DRC passed:

 

 

  

Here is a link to download the zip file of my Cadence simulations, layouts, and schematics: Lab_7.zip

 

I will backup all of my work onto my OneDrive and my desktop.

 

 

 

 

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