Lab 6 - EE 421L
Tyler Ferreira,
ferret1@unlv.nevada.edu
October 25, 2016
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Cadence Tutorial 4 seen here.
- Read through the lab in its entirety before starting to work on it
Experiment 1: NAND gate
First I will draft a schematic for a 2-input NAND gate using 6u/0.6u MOSFETS:
Now I will create a symbol to represent this circuit in order to use it later:
Now that I have a schematic and symbol for my NAND gate I will create a layout:
This layout represents a 2-input NAND gate. I can now DRC and LVS my layout:
Experiment 2: XOR Gate
First I will draft a schematic for a 2-input XOR gate using 6u/0.6u MOSFETS:
Now I will create a symbol for the XOR gate for use in the full adder schematic:
I will now create a layout for the XOR gate:
I will run DRC and LVS verifications on the above layout and schematic:
Now that the layouts of my NAND gate and XOR gate are finished I can simulate the operation of all of my gates.
I will create a schematic to test the outputs of my inverter from tutorial 3, my NAND gate, and my XOR gate:
In
my schematic I will test every 2-bit binary combination by using 2
pulse sources with different periods and pulse widths. This will ensure
that
I will obtain 00, 01, 10, and 11 binary numbers.
In
the simulation we can see that the XOR waveform has a dip in between
the 2 logic high values. This is caused by the timing of the pulses
and
the rise/fall time of each source. In reality each source will switch
from low to high or high to low and when this happens the output will
stay
the same but for that instant they change the output voltage will drop.
Experiment 3: Full Adder
Now
that I know all of my gates work as intended I can use them to design a
full adder circuit. First I will create the schematic for a full adder
circuit:
I can create a symbol for this schematic:
Now
that I have the symbol for my full adder I can use it to simulate the
operation of the circuit. Here is the schematic that I used to test the
operation of my circuit:
Each pulse source has a different period and pulse width in order to achieve every binary number from 0 to 7.
As
you can see in the simulation above my full adder circuit is operating
correctly. The outputs follow the truth table shown below.
| a | b | cin | s | cout |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Now that I know that the full adder circuit is operating correctly I can layout my circuit.
I can DRC and LVS my layout to make sure the layout matches my schematic:
Here is a link to download the zip file of my Cadence simulations, layouts, and schematics: Lab_6.zip
I will backup all of my work onto my OneDrive and my desktop.
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