Lab 5 - EE 421L
Tyler Ferreira,
ferret1@unlv.nevada.edu
October 4, 2016
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Tutorial 3 seen here.
Experiment 1:
Draft a schematic, layout, and symbol for a CMOS inverter using a 12u/0.6u PMOS and 6u/0.6u NMOS.
Schematic and symbol of the CMOS inverter:
Layout of the CMOS inverter using the C5 process:
Now I will DRC and LVS the layout:
Experiment 2:
Draft a schematic, layout, and symbol for a CMOS inverter using a 48u/0.6u PMOS and 24u/0.6u NMOS both with a multiplier of 4.
Schematic and symbol of the CMOS inverter:
Layout of the CMOS inverter using the C5 process:
Now I will DRC and LVS the layout:
Experiment 3:
I
will now use my 12u/6u CMOS inverter to simulate a circuit using the
Spectre and UltraSim simulators. I will use various capacitive loads to
understand
how the load will affect my circuit.
Here is a picture of the schematic used to perform these simulations (the load will change depending on the simulation):
| Spectre | UltraSim |
100fF Load | 
100fF Load |
1pF Load | 
1pF Load |
10pF Load | 
10pF Load |
100pF Load | 
100pF Load |
Experiment 4:
I
will now use my 48u/24u CMOS inverter to simulate a circuit using the
Spectre and UltraSim simulators. I will use various capacitive loads to
understand
how the load will affect my circuit.
Here is a picture of the schematic used to perform these simulations (the load will change depending on the simulation):
| Spectre | UltraSim |
100fF Load | 
100fF Load |
1pF Load | 
1pF Load |
10pF Load | 
10pF Load |
100pF Load | 
100pF Load |
We can see in experiments 3 and 4 that since this is an inverter, the output voltage is inverted
for every case.
We
also notice that as the capacitive load increases
the time delay increases. In every simulation as the capacitive load
increases we see that it takes more time to reach 50% of Vin.
In
the 12u/6u inverter we see that the load will affect the output voltage
at much smaller loads compared to the 48u/24u inverter.
Here is a link to all of my schematics and simulations used for this lab: Lab_5.zip
I have backed up all of my work onto my desktop as well as my OneDrive:
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