Lab 4 - EE 421L
Tyler Ferreira,
ferret1@unlv.nevada.edu
September 27, 2016
Pre-lab work- Back-up all of your work from the lab and the course.
- Read through this lab before starting it.
- Go through Tutorial 2 seen here.
- In
the simulations in this lab the body of all NMOS devices (the
substrate) should be at ground (gnd!) and the body of all PMOS devices
(the n-well) should be at a vdd! of 5V.
Lab work
Experiment
1: Plot the IV characteristic curves of an NMOS device and a PMOS
device for variations in gate, drain, and source voltage.
Schematic for simulating ID vs VDS | 
ID vs VDS for NMOS device
VDS = 0 to 5V in 1mV steps |
Schematic for simulating ID vs VGS with fixed VDS | 
ID vs VGS for NMOS device
VDS = 100mv |
Schematic for simulating ID vs VSD | 
ID vs VSD for PMOS device
VSD = 0 to 5V in 1mV steps |
Schemtatic for simulating ID vs VSG with fixed VSD | 
ID vs VSG for PMOS device
VSD = 100mV |
Experiment 2: Layout a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads.
Here is my layout for the NMOS connected to 4 probe pads:
Running the design rule check on the layout:
Creating a schematic to use with the extracted view of the layout to run layout versus schematic verification:
Running the LVS verification:
Experiment 3: Layout a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads.
Here is my layout for the PMOS connected to 4 probe pads:
Running the design rule check on the layout:
Creating a schematic to use with the extracted view of the layout to run layout versus schematic verification:
Running the LVS verification:
All of my lab work will be backed up on my OneDrive as well as my desktop.
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