Lab 07 – EE 421L
EsplinC2@UNLV.Nevada.edu
Pre-Lab Tasks
- Back-up
all of your work from the lab and the course.
- Go
through Tutorial 5 seen here.
Using buses and arrays in the design of word inverters,
muxes, and high-speed adders
Experiment(s):
- Draft
schematic, symbol, and simulations driving capacitive loads for the 4-Bit
word inverter having sizes of:
- 6u/6u
(= width of the PMOS / width of the NMOS with both devices having minimum
lengths of 0.6u)
o All four inverters' inputs are tied together to an input pulse source.
o The out<0> is not connected to a load while out<3> is
connected to a 100fF load.
o The out<1> is connected to a 1 pF load while out<2> is
connected to a 500 fF load.
o Show,
in your lab report, how a capacitive load influences the delay and rise/fall times.
·
Create schematics and
symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR
gates. Notice that power is run on the top of the cell via metal1 and ground is
run on the bottom of the cell also via metal1
- Provide a few simulation examples using these gates.
·
Next examine the
schematic of a 2-to-1 DEMUX/MUX (and symbol).
o Simulate the operation of this circuit
o Discuss the results and explain how the circuit can be used for
both multiplexing and de-multiplexing
·
Create an 8-bit wide word 2-to-1 DEMUX/MUX
schematic and symbol.
o Include
an inverter in your design so the cell only needs one select input, S (the
complement, Si, is generated using an inverter).
o Use
simulations to verify the operation of your design.
·
Draft the schematic of the full-adder seen in
Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
o Create
an adder symbol for this circuit (see the symbol used in lab6).
o Use
this symbol to draft an 8-bit adder schematic and symbol.
o For
how to label the bus so the carry out of one full-adder goes to the carry in of
another full-adder review the ring oscillator schematic discussed in Cadence
Tutorial 5.
o Simulate
the operation of your 8-bit adder.
o Lay
out this 8-bit adder cell
o Show
that your layout DRCs and LVSs correctly.
Results:
Draft
schematic, symbol, and simulations driving capacitive loads for the 4-Bit word
inverter
|
Schematic |
Symbol |
|
|
|
|
Simulation
Schematic |
|
|
|
|
Create schematics and
symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR
gates. Notice that power is run on the top of the cell via metal1 and ground is
run on the bottom of the cell also via metal1
NAND
|
Schematic |
Symbol |
|
|
|
|
8-Bit Schematic |
8-Bit Symbol |
|
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|
NOR
|
Schematic |
Symbol |
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8-Bit Schematic |
8-Bit Symbol |
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AND
|
8-Bit Schematic |
8-Bit Symbol |
|
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|
Or
|
8-Bit Schematic |
8-Bit Symbol |
|
|
|
Logic Gate Simulation Results
Schematic of a 2-to-1 DEMUX/MUX and symbol
|
Schematic |
Symbol |
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Create an 8-bit
wide word 2-to-1 DEMUX/MUX schematic & symbol
Use simulations to verify the operation of your
design.
|
Schematic |
Symbol |
|
|
|
Draft the schematic of the full-adder seen in Fig.
12.20 using 6u/0.6u devices (both PMOS and NMOS).
Full Adder
|
Schematic |
Symbol |
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Layout |
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8-Bit Schematic |
8-Bit Symbol |
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Layout |
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LVS |
DRC |
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