Lab 06 – EE 421L

Authored by Chandon Esplin,

EsplinC2@UNLV.Nevada.edu

10/26/2016 

Design, layout, and simulation of a CMOS NAND gate, XOR, and Full-Adder

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Pre-lab work

• Back-up all your work from the lab and the course.
• Go through Cadence Tutorial 4 seen here.
• Read through the lab in its entirety before starting to work on it

Design, layout, and simulation of a CMOS NAND gate, XOR, and Full-Adder

Experiment(s):

• Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
• Create layout and symbol views for these gates showing that the cells DRC and LVS without errors
• ensure that your symbol views are the commonly used symbols (not boxes!) for these gates with your initials in the middle of the symbol  
• ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
• use a standard cell height taller than you need for these gates so that it can be used for more complicated layouts in the future
• ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1
• Use cell names that include your initials and the current year/semester, e.g. NAND_jb_f19 (if it were fall 2019)
• Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11)  
• comment on how timing of the input pulses can cause glitches in the output of a gate
• Your html lab report should detail each of these efforts
• Using these gates, draft the schematic of the full adder seen below 
• Create a symbol for this full-adder (example)
• Simulate, using Spectre, the operation of the full-adder using this symbol  
• Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
• full-adder inputs and outputs can be on metal2 but not metal3
• DRC and LVS your full adder design 

Results:

Draft the schematics of a 2-input NAND gate and a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)

2 Input NAND Gate	2 Input XOR Gate

Create layout and symbol views for these gates showing that the cells DRC and LVS without errors

NAND Symbol	XOR Symbol
NAND Extracted	XOR Extracted
NAND Layout	XOR Layout
NAND DRC	XOR DRC
NAND LVS	XOR LVS

Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11)

Gate Simulation Schematic	Simulation Results

Discussion:

Comment on how timing of the input pulses can cause glitches in the output of a gate

As can be viewed in both simulation results, glitches may occur when transitioning from zero to one (on/off) or vice versa. If the simulation was altered to longer rise/fall times or if the periods of the inputs did not match up correctly, both of which reflect non ideal time delay, these minor glitches viewed above could have drastic effects on the output signals.

Using these gates, draft the schematic of the full adder

Create a symbol for this full-adder. Simulate, using Spectre, the operation of the full-adder using this symbol

Full Adder Schematic	Full Adder Symbol
Full Adder Simulation Schematic	Full Adder Simulation Results

Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed

DRC and LVS your full adder design

Full Adder Layout

F.A. Extracted	F.A. DRC	F.A. LVS

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